MagnaChip HMS39C7092, User Manual, Page: 48 / 197

BUS Controller Flash MCU(HMS39C7092)
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3.4 Basic Bus Interface
3.4.1 Overview
The HMS39C7092 has only a basic interface that allows direct connection of ROM,
SRAM, off-chip peripheral devices and so on.
3.4.2 Byte Lane Write Control
Data size for the CPU and other internal masters are byte(8-bit), half-word(16-bit),
word(32-bit). The bus controller has a data alignment function, and when accessing
external space, controls whether the upper data bus ( D
15
to D
8
) or lower data bus ( D
7
to D
0
) is used according to the bus specifications for the area being accessed (8-bit
access area or 16-bit access area) and the data size.
8-Bit Access Areas: Figure 3.3 shows data alignment control for 8-bit access space.
With 8-bit access space, the lower data bus ( D
7
to D
0
) is always used for accesses.
The amount of data that can be accessed at one time is one byte: a half-word access
is performed as two byte accesses, and a word access, as four byte accesses.
Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area)
Byte size
Half-word size
Word size
Lower Byte
1st bus cycle Lower Byte
2nd bus cycle Upper Byte
1st bus cycle LL Byte
2nd bus cycle LU Byte
3rd bus cycle UL Byte
4th bus cycle UU Byte