MagnaChip HMS39C7092, User Manual, Page: 129 / 197

Flash MCU(HMS39C7092) UART
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Status Register. In the FIFO mode this error is associated with the
particular character in the FIFO where it applies to. This error is revealed to
the CPU when its associated character is at the top of the FIFO. The UART
will try to resynchronize after a framing error. To do this, it assumes that the
framing error was due to the next start bit, so it samples this ìstartî bit twice
and then takes it in the ìdataî.
BI This bit is the Break Interrupt indicator. Bit 4 is set to ë1í whenever the
received data input is held in the Spacing (logic 0) state for longer than a
full word transmission time (that is, the total time of Start bit + data bits +
Parity + Stop bits). The BI indicator is reset whenever the CPU reads the
contents of the Line Status Register. In the FIFO mode this error is
associated with the particular character in the FIFO where it applies to.
This error is revealed to the CPU when its associated character is at the
top of the FIFO. When break occurs only one zero character is loaded into
the FIFO. The next character transfer is enabled after SIN goes to the
marking state and receives the next valid start bit.
** Note : Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any
of the corresponding conditions is detected and the interrupt is enabled.
THRE This bit is the Transmitter Holding Register Empty indicator. Bit 5 indicates
that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to the CPU when
the Transmit Holding Register Empty Interrupt enable is set to high. The
THRE bit is set to ë1í when a character is transferred from the Transmitter
Holding Register into the Transmitter Shift Register. The bit is reset to ë0í
concurrently with the loading of the Transmitter Holding Register by the
CPU. In the FIFO mode this bit is set when the XMIT FIFO is empty; it is
cleared when at least 1 byte is written to the XMIT FIFO.
TEMT This bit is the Transmitter Empty indicator. Bit 6 is set to ë1í whenever the
Transmitter Holding Register (THR) and the Transmitter Shift Register
(TSR) are both empty. It is reset to ë0í whenever either the THR or TSR
contains a data character. In the FIFO mode this bit is set to one whenever
the transmitter FIFO and register are both empty.
FIFOE In the 16450 mode, this is 0. In the FIFO mode, FIFOE is set when there is
at least one parity error, framing error or break indication in the FIFO.
LSR7 is cleared when the CPU reads the LSR, if there are no subsequent
errors in the FIFO.
** Note : The Line Status Register is intended for read operations only.