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MagnaChip HMS39C7092 User Manual Download Page 165

 
 

Flash

 

MCU(HMS39C7092)

 

 

On-chip

 

Flash

 

memory

 

 

 

165

 

 

 

FMPR=0x12

 

wait

 

for

 

2us

 

FMCR=0x02

 

wait

 

for

 

10us

 

FMCR=0x0A

 

wait

 

for

 

T_ERASE

 

FMCR=0x00

 

FMPR=0x00

 

wait

 

for

 

20us

 

ptr

Å

start

 

of

 

block

 

FMCR=0x10

 

wait

 

for

 

10us

 

(ptr)

Å

0xffff

 

wait

 

for

 

2us

 

(ptr)==0xFFFF

 

&&ptr<end

 

of

 

block?

Trial

 

Count=0

 

ptr+=2

 

ptr==endaddress?

(verify

 

is

 

OK?)

 

FMCR=0x00

 

wait

 

for

 

2us

 

Trial

 

Count++

 

Trial

 

Count<20?

 

OK

 

Fail

 

Erase

 

Phase

 

Verify

 

Phase

 

FEBR=erase

 

sector

 

*T_ERASE

 

=

 

min

 

100us

 

 

Figure

 

12.7

   

Flash

 

Erase

 

&

 

Erase

 

Verify

 

Sequence

 

Summary of Contents for HMS39C7092

Page 1: ...HMS39C7092 32Bit Embedded Flash MCU User s Manual Version 1 2...

Page 2: ...ications of our products No responsibility is assumed by Magnachip for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implicat...

Page 3: ...structions 39 Chapter 3 41 BUS Controller 41 3 1 Overview 42 3 1 1 Features 42 3 1 2 Pin Configuration 43 3 2 Bus Controller Registers 44 3 2 1 Configuration Registers 45 3 3 Operation 46 3 3 1 Area D...

Page 4: ...g Timer Register Descriptions 91 7 6 Examples of Register Setting 94 7 6 1 Interval Timer Mode 94 7 6 2 Watchdog Timer Mode with Internal Reset Disable 95 7 6 3 Watchdog Timer Mode with Power on Reset...

Page 5: ...General Description 146 12 2 Features 146 12 3 Block Diagram 148 12 4 Flash Memory Register Description 150 12 5 On Board Programming Mode 155 12 5 1 Boot Mode 155 12 5 2 User Program Mode 158 12 6 Fl...

Page 6: ...aximum Ratings 187 14 2 Recommended Operating Conditions 187 14 3 DC Characteristics 188 14 4 AC Characteristics 189 14 4 AD Conversion characteristics 191 14 5 Operational Timing 192 14 5 1 Clock Tim...

Page 7: ...ontrol Signal Read Timing for 16 Bit 1 Wait Byte Access 52 Figure 3 11 Bus Control Signal Write Timing for 16 Bit 2 Wait Word Access 53 Figure 3 12 Bus Control Signal Read Timing for 16 Bit 2 Wait Wor...

Page 8: ...ion Procedure 158 Figure 12 5 Flash Program Program Verify Sequence 161 Figure 12 6 Flash Pre program Pre program Verify Sequence 163 Figure 12 7 Flash Erase Erase Verify Sequence 165 Figure 12 8 Flas...

Page 9: ...t Controller 81 Table 6 3 Interrupt Source Trigger Mode 82 Table 7 1 Memory Map of the Watchdog Timer APB Peripheral 90 Table 7 2 Internal Counter Clock Sources 92 Table 8 1 Timer Global Control Regis...

Page 10: ...176 Table 14 1 Absolute Maximum Ratings 187 Table 14 2 Recommended Operating Conditions 187 Table 14 3 DC Characteristics 188 Table 14 4 IO Circuits with pull ups 188 Table 14 5 IO Circuits with pull...

Page 11: ...Flash MCU HMS39C7092 11...

Page 12: ...Flash MCU HMS39C7092 12...

Page 13: ...Flash MCU HMS39C7092 Introduction 13 Chapter 1 Introduction...

Page 14: ...5 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 HMS39C7092 2001 02 A13 P25 A12 P24 A11 P23 A10 P22 A9 P21 A8 P20 VSS A7 P17 A6 P16 A5 P15 A4 P14 A3 P13 A2...

Page 15: ...er 8 external sources Six 16bit Multifunction Timer PWMs for General Purpose Applications One 8bit Watch Dog Timer WDT Two UARTs Universal Asynchronous Receiver Transmitter compatible with 16C550 UART...

Page 16: ...neral purpose input output of port B bit5 TDI I JTAG Test Data Input 8 PB6 I O General purpose input output of port B bit6 TCK I JTAG Test Clock 9 PB7 I O General purpose input output of port B bit7 1...

Page 17: ...5 D14 I O External Data Bus bit 14 33 P36 I O General purpose input output or port 3 bit 6 D15 I O External Data Bus bit 15 34 P37 I O General purpose input output or port 3 bit 7 35 VDD Power Supply...

Page 18: ...cycle wait signal 58 P60 I O General purpose input output of port 6 bit 0 nBREQ I External BUS Request 59 P61 I O General purpose input output of port 6 bit 1 nBACK I External BUS Acknowledge 60 P62 I...

Page 19: ...output of port 8 bit 1 nCS2 O External Chip Selection Number 2 nIRQ2 I External Interrupt Request number 2 89 P82 I O General purpose input output of port 8 bit 2 nCS1 O External Chip Selection Number...

Page 20: ...Ch1 98 PA5 I O General purpose input output of port A bit 5 A21 O External Address Bus bit 21 TIOCA2 I O PWM output Compare match output of Reg A and signal capture input of Timer Ch2 99 PA6 I O Gener...

Page 21: ...ory remap for appropriate mode Figure 1 3 shows default memory map and the memory maps of respective modes are shown in Figure 1 4 Figure 1 5 and Figure 1 6 The Mode definition is listed as follows Ta...

Page 22: ...UART boot mode MICOM mode 1 VDD 2 nCS7 TIOCA3 3 nCS6 TIOCB3 4 nCS5 TIOCA4 5 nCS4 TIOCB4 6 TMS 7 TDO 8 TDI 9 TCK 10 TVPPD 11 VSS 12 TxD0 13 RxD0 14 TxD1 15 RxD1 16 nIRQ4 17 nIRQ5 18 D0 P40 19 D1 P41 2...

Page 23: ...ode UART boot mode MICOM mode 41 A5 P15 42 A6 P16 43 A7 P17 44 VSS 45 A8 P20 46 A9 P21 47 A10 P22 48 A11 P23 49 A12 P24 50 A13 P25 51 A14 P26 52 A15 P27 53 A16 P50 54 A17 P51 55 A18 P52 56 A19 P53 57...

Page 24: ...S External 16bit BUS Flash boot mode with 16bit BUS UART boot mode with 16bit BUS Flash boot mode MICOM mode UART boot mode MICOM mode 81 AN3 82 AN4 83 VSS 84 TIOCA5 85 TIOCB5 86 P75 87 nIRQ0 88 nCS3...

Page 25: ...0 nCS2 0x002F FFFF 0x0020 0000 nCS3 0x003F FFFF 0x0030 0000 nCS4 0x004F FFFF 0x0040 0000 nCS5 0x005F FFFF 0x0050 0000 nCS6 0x006F FFFF 0x0060 0000 nCS7 0x007F FFFF 0x0070 0000 Reserved 0x07FF FFFF 0x0...

Page 26: ...0x0000 1000 FLASH 192KB 0x0002 FFFF 0x0000 0000 FLASH 192KB 0x0002 FFFF 0x0000 0000 On Chip SRAM 4KB 0x0000 0FFF 0x0000 0000 On Chip SRAM 4KB 0x0000 0FFF 0x0000 0000 nCS0 0x000F FFFF 0x0000 0100 nCS1...

Page 27: ...Flash MCU HMS39C7092 ARM7TDMI Core 27 Chapter 2 ARM7TDMI Core...

Page 28: ...sity of standard ARM code while retaining most of the ARM s performance advantage over a traditional 16bit processor by using 16bit registers This is possible because THUMB code operates on the same 3...

Page 29: ...n c r e m e n t e r b u s 32 x 8 Multiplier Barrel Shifter 32 bit ALU Write Data Register B b u s A b u s Instruction Pipeline Read Data Register Thumb Instruction Decoder nENOUT nENIN DBE D 31 0 Cor...

Page 30: ...L Rn Rd 0 0 0 0 1 S H 1 Rm Halfword Data Transfer register offset Cond 0 0 0 P U 1 W L Rn Rd Offset 1 S H 1 Offset Halfword Data Transfer immediate offset Cond 0 1 I P U B W L Rn Rd Offset Single Data...

Page 31: ...ess MCR Move CPU register to coprocessor register cRn rRn op cRm MLA Multiply Accumulate Rd Rm Rs Rn MOV Move register or constant Rd Op2 MRC Move from coprocessor register to CPU register Rn cRn op c...

Page 32: ...R6 R6 R7 R7 R7 R7 R7 R7 R8 R8_fiq R8 R8 R8 R8 R9 R9_fiq R9 R9 R9 R9 R10 R10_fiq R10 R10 R10 R10 R11 R11_fiq R11 R11 R11 R11 R12 R12_fiq R12 R12 R12 R12 R13 R13_fiq R13_svc R13_abt R13_irq R13_und R14...

Page 33: ...Offset 8 0 1 0 1 H S 1 Ro Rb Rd Load store sign extended byte halfword 9 0 1 1 B L Offset5 Rb Rd Load store with immediate 10 1 0 0 0 L Offset5 Rb Rd Load store halfword 11 1 0 0 1 L Rd Word8 SP relat...

Page 34: ...V V CMP Compare V V V EOR EOR V V LDMIA Load multiple V LDR Load word V LDRB Load byte V LDRH Load halfword V LSL Logical Shift Left V V LDSB Load sign extended byte V LDSH Load sign extended Halfwor...

Page 35: ...svc LR_abt LR_irq LR_und PC PC PC PC PC PC THUMB state Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und banked register Figure 2 5 Register Organizat...

Page 36: ...Z set OR N not equal to V less than or equal 1110 AL Ignored always 2 4 3 The Program Status Registers The ARM7TDMI contains Current Program Status Register CPSR plus five Saved Program Status Regist...

Page 37: ...is executing in ARM state Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits The I and F...

Page 38: ...0 R14_fiq R8_fiq PC CPSR SPSR_fiq 10010 IRQ R7 R0 LR_irq SP_irq PC CPSR SPSR_irq R12 R0 R14_irq R13_irq PC CPSR SPSR_irq 10011 Supervisor R7 R0 LR_svc SP_svc PC CPSR SPSR_svc R12 R0 R14_svc R13_svc PC...

Page 39: ...Flash MCU HMS39C7092 ARM7TDMI Core 39 2 4 4 ARM Instructions Refer to ARM7TDMI Datasheet ARM DDI 0029E...

Page 40: ...BUS Controller Flash MCU HMS39C7092 40...

Page 41: ...Flash MCU HMS39C7092 BUS Controller 41 Chapter 3 BUS Controller...

Page 42: ...each area In THUMB mode only 16 bit accessing of external code memory is allowed Active low chip select signals nCS0 to nCS7 can be output for area 0 to 7 Bus specifications can be set independently...

Page 43: ...s bus nRD O Strobe signal indicating reading from the external address space nHWR O Strobe signal indicating writing to the external address space with valid data on the upper data bus D15 to D8 nLWR...

Page 44: ...Register 0x10F BCR1 0x0104 R W CS1 Bus Configuration Register 0x0 BCR2 0x0108 R W CS2 Bus Configuration Register 0x0 BCR3 0x010C R W CS3 Bus Configuration Register 0x0 BCR4 0x0110 R W CS4 Bus Configur...

Page 45: ...ode3 0x0000 BCR1 7 ExtWaitEn Enable external nWAIT signal input 0 disable external nWAIT signal input 1 enable external nWAIT signal input MemWidth Select the size of the external bus width 0 16 bit e...

Page 46: ...BCR0 to BCR7 0x000F FFFF 0x001F FFFF 0x002F FFFF 0x003F FFFF 0x004F FFFF 0x005F FFFF 0x006F FFFF 0x007F FFFF nCS1 nCS2 nCS3 nCS4 nCS5 nCS6 nCS7 Reserved 0x07FF FFFF a 16 Mbyte modes Default SM 0 in t...

Page 47: ...ns as a 16 bit access space If all areas are designed for 8 bit access 8 bit bus mode is set if any area is designed for 16 bit access 16 bit bus mode is set Number of Wait States One to 16 wait state...

Page 48: ...ording to the bus specifications for the area being accessed 8 bit access area or 16 bit access area and the data size 8 Bit Access Areas Figure 3 3 shows data alignment control for 8 bit access space...

Page 49: ...ta Alignment Control 16 Bit Access Area nHWR nLWR signals are generated according to the memory transfer width external memory width A0 and the access sequencing The following table shows the basic co...

Page 50: ...s control signals for a 16 Bit 1 wait access area In case of 32 bit word access In this case the NormWait value in BCR of this area is 0 Note Sequential read access keeps nRD signal to LOW state Figur...

Page 51: ...3 8 shows the read timing of bus control signals for a 16 Bit 1 wait access area In case of half word access Figure 3 7 Bus Control Signal Write Timing for 16 Bit 1 Wait Half word Access Figure 3 8 Bu...

Page 52: ...ure 3 10 shows the read timing of bus control signals for a 16 Bit 1 wait access area In case of byte access Figure 3 9 Bus Control Signal Write Timing for 16 Bit 1 Wait Byte Access Figure 3 10 Bus Co...

Page 53: ...ows the read timing of bus control signals for a 16 Bit 2 wait access area In case of word access Figure 3 11 Bus Control Signal Write Timing for 16 Bit 2 Wait Word Access Figure 3 12 Bus Control Sign...

Page 54: ...3 14 shows the read timing of bus control signals for a 16 Bit 2 wait access area In case of half word access Figure 3 13 Bus Control Signal Write Timing for 16 Bit 2 Wait Half Word Access Figure 3 14...

Page 55: ...ure 3 16 shows the read timing of bus control signals for a 16 Bit 2 wait access area In case of byte access Figure 3 15 Bus Control Signal Write Timing for 16 Bit 2 Wait Byte Access Figure 3 16 Bus C...

Page 56: ...al basis in each access space according to the settings of NormWait bit fields in BCR0 7 Pin Wait Insertion When external space is accessed in this state a program wait is first inserted If the nWAIT...

Page 57: ...as the right the bus arbiter transfers the bus right to the bus master that requested it The bus right is transferred at the following times z The bus right is transferred at the boundary of a bus cyc...

Page 58: ...er during a read cycle in a 1 wait state access area There is a minimum interval of three states from when the nBREQ signal goes low until the bus is released Figure 3 18 Example of External Bus Maste...

Page 59: ...Flash MCU HMS39C7092 MCU controller 59 Chapter 4 MCU Controller...

Page 60: ...CB3 P51 A17 PB2 nCS5 TUICA4 P52 A18 PB3 nCS4 TIOCB4 Port 5 P53 A19 PB4 TMS P60 nWAIT PB5 TDO P61 nBREQ PB6 TDI P62 nBACK Port B PB7 TCK P63 nAS P10 A0 P64 nRD P11 A1 P65 nHWR P12 A2 P66 nLWR P13 A3 Po...

Page 61: ...ort 3 P4MR 0x0014 R W Pin MUX Control Register for Port 4 P5MR 0x0018 R W Pin MUX Control Register for Port 5 P6MR 0x001C R W Pin MUX Control Register for Port 6 P7MR 0x0020 R W Pin MUX Control Regist...

Page 62: ...ed PA4 00 A23 01 TIOCA1 10 PA4 11 reserved PA3 00 TCLKD 01 TIOCB0 10 PA3 11 reserved PA2 00 TCLKC 01 TIOCA0 10 PA2 11 reserved PA1 0 TCLKB 1 PA1 PA0 0 TCLKA 1 PA0 PBMR Port B Multiplex Register 0x0900...

Page 63: ..._000C R W b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 P2MR Reserved P27 P26 P25 P24 P23 P22 P21 P20 Initial value depend on operating mode refer to Table 4 3 P27 0 A15 1 P27 P26 0 A14 1 P26 P25 0 A13 1 P25 P24 0 A...

Page 64: ...Multiplex Register 0x0900_0018 R W b31 b4 b3 b2 b1 b0 P5MR Reserved P53 P52 P51 P50 Initial value depend on operating mode refer to Table 4 3 P53 0 A19 1 P53 P52 0 A18 1 P52 P51 0 A17 1 P51 P50 0 A16...

Page 65: ..._0024 R W b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 P8MR Reserved P84 P83 P82 P81 P80 Initial value depend on operating mode refer to Table 4 3 P84 0 CS0 1 P84 P83 00 CS1 01 IRQ3 10 P83 11 reserved P82 00 CS2 01...

Page 66: ...MCU controller Flash MCU HMS39C7092 66 4 3 3 MCU Device Code Register 0x0900_002C Read Only This Register is read only Device Code Value is 0x3943_7092...

Page 67: ...Flash MCU HMS39C7092 Power Management Unit 67 Chapter 5 Power Management Unit...

Page 68: ...ower down modes control Clock Control Register RESET Filter RESET Generator PMU State Machine PIN MUX TEST MODE 1 2 RESET Filter nRESET MODE 2 0 XOUT XIN SCLK_GEN CLKIN SCLK BCLK MUX CLKOUT Internal S...

Page 69: ...m well defined modes of operation RUN Power down mode 5 2 2 Reset and Operation Modes A set of four useful states or modes is defined as follows RESET When it is power on watchdog timer overflow watch...

Page 70: ...ASB and APB so the power consumption of system is dramatically low Although MCU is in the power down mode user can set interrupt controller block working in the power down mode Wake up from the Powe...

Page 71: ...Register Map of the PMU Name I O Offset DIR Description PMUCR 0x1000 W PMU operation mode controls register PMUSR 0x1000 R PMU status register shows the just previous PMU state PCLKCR 0x1008 R W Perip...

Page 72: ...ue is initialized by Run State 00 If PMUCR is 3 device enters the PD Power Down mode The other values don t effect The address of register is 0x0900_1000 PMUST PMU Status Register 0x0900_1000 Read Onl...

Page 73: ...rrupt controller clock control register 0 Interrupt controller use the XIN clock XIN is not killed at any mode 1 Interrupt controller use the BCLK of internal Bus clock The Bus clock is killed when Po...

Page 74: ...On Flash Re mapping of Flash start address to 0x0 in MODE 6 and 7 0 Default value 1 Re mapping of Flash start address to 0x0 in the memory map It is valid at MODE 6 and 7 REMAP Re map internal SRAM a...

Page 75: ...PMU signal timing is as shown below 5 5 1 Power on Reset Figure 5 3 Power on Reset Timing Diagram 5 5 2 Watch Dog Timer Overflow Figure 5 4 Watch Dog Timer Overflow Timing Diagram BCLK WDTOVF IN Inte...

Page 76: ...es The first Soft Reset operation is switched by MAN_RST signal from WDT Another case is from PMU reset control register Figure 5 5 Soft Reset from WDT Timing Diagram Figure 5 6 Soft Reset from PMU Ti...

Page 77: ...Flash MCU HMS39C7092 Interrupt controller 77 Chapter 6 The Interrupt Controller...

Page 78: ...ach interrupt source and output signal Selection of the output paths IRQ or FIQ for each interrupt source Mask Control IRQ source0 IRQ source20 IRQ source1 IRQ source2 IRQ source3 IRQ source4 IRQ sour...

Page 79: ...T19 Timer 5 INT20 Software Interrupt The Users can set the active mode of all interrupt source inputs The default mode is the falling edge trigger mode Any inversion or latching required to providing...

Page 80: ...ter is used to reflect the status of all channels set to produce an FIQ interrupt or IRQ interrupt And the status registers are cleared by writing 1 to the ISCR register in edge trigger mode only Bit...

Page 81: ...rupt input sources and defines which active sources will generate an interrupt request to the processor If certain bits within the interrupt controller are not implemented the corresponding bits in th...

Page 82: ...hat the interrupt is configured to rising active for edge trigger mode and to high active for level trigger mode On reset all interrupt input sources are configured to falling low active Table 6 3 Int...

Page 83: ...Initial value 0x00000000 Bit field I0 I24 1 IRQ Pending 0 IRQ Idle The IRQ status register is used to reflect the status of all channels set to produce an IRQ interrupt IDR i 0 When an interrupt is s...

Page 84: ...ts are unmasked ISCR Interrupt Status Clear Register 0x0900_1220 Write Only b31 b21 b20b19b18b17b16b15b14b13b12b11b10 B9 b8 b7 b6 b5 B4 b3 b2 b1 b0 ISCR Reserved I20 I19 I18 I17 I16 I15 I14 I13 I12 I1...

Page 85: ...Flash MCU HMS39C7092 Watchdog Timer 85 Chapter 7 Watchdog Timer...

Page 86: ...Unit eight counter clock sources selection whether to reset the chip internally or not two types of reset signal power on reset and manual reset WTCNT Timer Counter 8 bit WTCR Timer Reset Control Reg...

Page 87: ...U a reset signal is output to PMU When this watchdog function is not needed the WDT can be used as an interval timer In the interval timer operation an interval timer interrupt is generated at each co...

Page 88: ...nd overflow due to a system crash or the like WDT Interrupt signal and Internal Manual RESET signal are output The INT_WDT signal is not output if INTEN is disabled INTEN 0 WTCNT value Time 0x00 0xFF...

Page 89: ...eration in the Interval Timer Mode 7 3 1 Timing of Setting and Clearing the Overflow Flag Timing of setting the overflow flag In the interval timer mode when the WTCNT overflows the ITOVF flag is set...

Page 90: ...ol the reset signal and test it The start address of the watchdog timer is fixed to 0x0900_1100 and the offset of any particular register from the base address is fixed Table 7 1 Memory Map of the Wat...

Page 91: ...Reset select register Select the type of generated internal reset if the WTCNT overflows in the watchdog timer mode 0 Power on reset 1 Manual reset RSTEN Reset enable register Select whether to reset...

Page 92: ...1 98 ms 1 31 ms 101 SYSCLK 512 3 97 ms 2 62 ms 110 SYSCLK 2048 15 88 ms 10 48 ms 111 SYSCLK 8192 63 55 ms 41 94 ms WRSR Reset Status Register 0x0900_1104 Read Only b31 b2 b1 b0 WRSR Reserved ITOVF WT...

Page 93: ...0 0 0 0 Initial value 0x 00 Bit field I0 I7 8 bit readable and writable upcounter When the timer is enabled the timer counter starts counting pulse of the selected clock source When the value of the...

Page 94: ...ister Setting 7 6 1 Interval Timer Mode WTCNT 0x00 WTCR 0xA0 WTCR WDT Interrupt WRSR Internal Reset Manual Reset WDT OVF WTCNT XIN WDT CLK FE FF 00 01 10 11 12 13 14 0 0 A0 A0 00 10 00 Read WRSR Regis...

Page 95: ...Internal Reset Disable WTCNT 0x00 normally WTCR 0xE0 WTCR WDT Interrupt WRSR Internal Reset Manual Reset WDT OVF WTCNT BCLK WDT CLK FE FF 00 01 10 11 12 13 14 00 01 0 0 E0 E0 Read WRSR Register 00 Fig...

Page 96: ...Timer Mode with Power on Reset WTCNT 0x00 WTCR 0xF0 WTCR WDT Interrupt WRSR Internal Reset Manual Reset WDT OVF WTCNT BCLK WDT CLK FE FF 00 01 10 11 12 00 00 01 00 0 F0 F0 0 Reset Figure 7 6 Interrupt...

Page 97: ...dog Timer Mode with Manual Reset WTCNT 0x00 WTCR 0xF8 WTCR WDT Interrupt WRSR Internal Reset Manual Reset WDT OVF WTCNT BCLK WDT CLK FE FF 00 01 10 11 12 13 14 00 01 00 0 0 F8 F8 Figure 7 7 Interrupt...

Page 98: ...Watchdog Timer Flash MCU HMS39C7092 98...

Page 99: ...Flash MCU HMS39C7092 General Purpose Timer 99 Chapter 8 The General Purpose Timer...

Page 100: ...clearing function at compare match or input capture mode Synchronizing mode PWM mode 18 interrupt sources Selectable 4 internal clock sources and 4 external clock sources Internal data bus Clock Gener...

Page 101: ...ssible to select one of eight counter clock sources for all channels Internal clock counting at falling edge BCLK 2 BCLK 4 BCLK 16 BCLK 64 External clock counting at falling edge There are five partic...

Page 102: ...0x1314 W test only 0x1318 R test only Table 8 2 Timer Channel Control Register Map REG I O OFFSET DIR DESCRIPTION TCR0 0x1320 R W Timer 0 Control Register TIOCR0 0x1324 R W Timer 0 I O Control Regist...

Page 103: ...able and writable register that starts and stops the counter of each channel TSYNCR Timer Sync Register 0x0900_1304 R W b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 TSYNCR Reserved res res SYNC5 SYNC4 SYNC3 SYNC2 S...

Page 104: ...0xXXXXXX98 CCLR Select the Counter clear condition 00 not cleared free running mode 01 cleared by GRA compare match or input capture periodic mode 10 cleared by GRB compare match or input capture per...

Page 105: ...B compare match 100 GRB captures the rising edge of input 101 GRB captures the falling edge of input 110 GRB captures both edge of input 111 Don t care IOA Select GRA Function 000 compare match with p...

Page 106: ...ls the enabling disabling of overflow interrupt request and the general register compare match input capture interrupt requests TIERn controls the interrupt enable disable TSR0 Timer 0 Status Register...

Page 107: ...dable and writable register There are 2 general registers for each channel total 12 Each general register can function as either an output compare register or an input capture register by setting it i...

Page 108: ...se Timer Unit Operation There are five particular operation mode which can be configured respectively The operation modes are described below Free Running Mode Compare Match Mode Input Capture Mode Sy...

Page 109: ...ng Periodic counter operation is obtained for a given channel s TCNT by selecting compare match as a TCNT clear source Set the GRA or GRB for period setting to output compare register and select count...

Page 110: ...General Purpose Timer Flash MCU HMS39C7092 110 Figure 8 3 Periodic Counter Operation Time TCNT value GR STR0 STR4 OVF 0x0000 Counter cleared by GR compare match...

Page 111: ...d the counter reached that value the channel generates interrupt and external output by user s setting The output value can be 1 0 or toggle value The counter can be cleared by user s setting when the...

Page 112: ...gure 8 5 Example of Toggle Output Figure 8 6 Compare Match Signal Output Timing Counter cleared at GRB compare match TCNT value GRB GRA TIOCB TIOCA Toggle output Toggle output Time CK TCNT input clock...

Page 113: ...tting the MCIAE or MCIBE in TIER the interrupt can be generated by the external capture event The capture data and interrupt are generated after 2 timer clocks If CCR field in TCR is appropriately set...

Page 114: ...r input capture the other channels can be cleared simultaneously When some channels are set to synchronization mode and user would write any value to one of them the other channels can be written with...

Page 115: ...r the timer counter All five channels can be set to PWM mode 8 3 5 1 PWM Mode Operation Figure 8 9 illustrates PWM mode operations When the PWM mode is set the TIOCA pin becomes the output pin Output...

Page 116: ...setting GRA to a larger value than GRB A 100 duty waveform can be obtained by setting the counter clear source to GRA and then setting GRB to a larger value than GRA Figure 8 10 PWM Mode Operation Exa...

Page 117: ...e reset synchronized PWM mode TCNT1 operates as an upcounter that is cleared to 0x0000 at compare match with GRA1 TCNT2 runs independently and is isolated from GRA2 and GRB2 The PWM waveform outputs t...

Page 118: ...General Purpose Timer Flash MCU HMS39C7092 118...

Page 119: ...Flash MCU HMS39C7092 UART 119 Chapter 9 UART Universal Asynchronous Receiver Transmitter...

Page 120: ...ion of the transfer operations performed by the UART as well as any error conditions parity overrun framing or break interrupt The UART includes a programmable baud rate generator that is capable of d...

Page 121: ...cs 5 6 7 or 8 bit characters Even odd or no parity bit generation and detection 1 1 5 or 2 stop bit generation and detection Baud generation DC to 256k baud False start bit detection Complete status r...

Page 122: ...RECEIVER FIFO LINE CONTROL REGISTER DIVISOR LATCH LS DIVISOR LATCH MS LINE STATUS REGISTER TRANSMITTER HOLDING REGISTER INTERRUPT ENABLE REGISTER INTERRUPT ID REGISTER FIFO CONTROL REGISTER RECEIVER...

Page 123: ...nsmitter Holding DLAB 0 IER 0x1404 R W Interrupt Enable IIR 0x1408 R Interrupt Identification FCR 0x1408 W FIFO Control LCR 0x140C R W Line Control LTR 0x1410 R W Loop Test Control LSR 0x1414 R W Line...

Page 124: ...ck is generated from the on chip clock generator If this bit is 0 then the clock generator stop to operate CLKDR Clock Divisor Register 0x1424 R W b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 CLKDR Reserved PRS Res...

Page 125: ...pecifies the number of Stop bits transmitted and received in each serial character If bit 2 is 0 one Stop bit is generated in the transmitted data If bit 2 is 1 when a 5 bit word length is selected vi...

Page 126: ...Divisor Latch Lower Byte b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 DLM Reserved DLM Reset 00 Initial value 0xXXXXXX00 DLM Divisor Latch Upper Byte The UART contains a programmable Baud Generator that is capable...

Page 127: ...r Values for each Baud rate CLK 36 864MHz 36 864 MHz Desired Baud Rate Decimal Divisor Value Prescaler Value Error Percentage 50 4608 10 110 2094 10 0 026 300 768 10 1200 192 10 2400 96 10 4800 48 10...

Page 128: ...ffer Register thereby destroying the previous character The OE indicator is set to 1 upon the detection of an overrun condition and reset whenever the CPU reads the contents of the Line Status Registe...

Page 129: ...eceiver Line Status interrupt whenever any of the corresponding conditions is detected and the interrupt is enabled THRE This bit is the Transmitter Holding Register Empty indicator Bit 5 indicates th...

Page 130: ...used to enable the FIFOs clear the FIFOs and set the RCVR FIFO to trigger level FIFOEN Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs Resetting FCR0 will clear all bytes in both FIFOs When...

Page 131: ...he IIR the UART freezes all interrupts and indicates the highest priority pending interrupt to the CPU While this CPU access occurs the UART records new interrupts but does not change its current indi...

Page 132: ...DEM Status Clear to Send Data Set Ready Ring Indicator or Data Carrier Detect Reading the MODEM Status Register IEN Interrupt Enable Register 0x1404 R W b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 IEN Reserved Res...

Page 133: ...state The receiver Serial Input SIN is disconnected the output of the Transmitter Shift Register is looped back into the Receiver Shift Register input The two flow control outputs nDTR and nRTS On the...

Page 134: ...er received was longer than 4 continuous character times if 2 stop bits are programmed the second one is included in this time delay the latest CPU read of the FIFO was longer than 4 continuous charac...

Page 135: ...trigger level interrupts have the same priority as the current received data available interrupt XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt 9 6...

Page 136: ...RBR 0x00 R RBR DLAB 0 THR 0x00 W THR DLAB 0 IER 0x04 R W RLSIE THREIE DRIE IIR 0x08 R FID IID IPEN FCR 0x08 W FIFODEPTH FCR2 FCR1 FIFOEN LCR 0x0C R W DLAB BREAK STICKP PARITY PEN STOPBIT DLEN LTR 0x10...

Page 137: ...Flash MCU HMS39C7092 GPIO 137 Chapter 10 GPIO General Purpose Input Output...

Page 138: ...P B I F P o rt A D a ta R e g P o rt A D ir R e g P o rt B D a ta R e g P o rt B D ir R e g P o rt B P o rt A E PA 7 0 PA 7 0 PA O E 7 0 E P B 7 0 P B 7 0 P B O E 7 0 P D 7 0 PA 7 2 B n R E S P S E L...

Page 139: ...ory Map REG I O OFFSET DIR DESCRIPTION PADR 0x1600 R W 8 bit Port A Data register PADDR 0X1604 R W Port A Data Direction register PBDR 0X1608 R W 8 bit Port B Data register PBDDR 0X160C R W Port B Dat...

Page 140: ...8 or 9 b31 b8 b7 b6 b5 b4 b3 b2 b1 b0 PnDR Reserved D7 D6 D5 D4 D3 D2 D1 D0 Reset 0 0 0 0 0 0 0 0 Initial value 0x 00 Bit field D0 D7 1 Pn bit is High 0 Pn bit is Low PnDDR Port n Data Direction Regi...

Page 141: ...ta Register and a Data Direction Register On reads the Data Register contains the current status of correspondent port pins whether they are configured as input or output Writing to a Data Register on...

Page 142: ...GPIO Flash MCU HMS39C7092 142...

Page 143: ...Flash MCU HMS39C7092 On Chip SRAM 143 Chapter 11 On Chip SRAM...

Page 144: ...data in the On chip RAM can always be accessed in one cycle that make the RAM ideal for use as a program area stack area or data area which requires high speed access The contents of the on chip RAM...

Page 145: ...Flash MCU HMS39C7092 On chip Flash memory 145 Chapter 12 On chip Flash Memory...

Page 146: ...as shown in Table 12 1 12 2 Features The features of the flash memory are summarized below Memory organization 96K x 16 bits 1 5Mbit Operating Voltage dual power 3 0V 3 6V Vcc 4 5 5 5V FTVPPD Random...

Page 147: ...bit data bus and 16 Mbyte address mode 0 1 1 M3 External 16 bit data bus and 16 Mbyte address mode 1 0 0 M4 Flash memory boot with external 16 bit data bus mode 1 0 1 M5 Flash memory boot mode microc...

Page 148: ...Block Diagram Figure 12 1 Block Diagram of Flash Memory BCLK BA 31 0 BD 31 0 BSIZE 1 0 MODE 2 0 nRESET FlashArray 96Kx16bits BWAIT Decoder Bus Interface Controller Wait Control WAITREG Test Logic Cont...

Page 149: ...rd or word BA 31 0 I System address bus BA 31 17 is used for selection between Internal Register Block and Flash Memory BA 16 0 is used for selection of Specific Internal Register or Flash Memory Addr...

Page 150: ...tus Power Register 0x0000 FMTR 0x0218 R W Test Register 0x0400 FMWR Wait Control Register Bit 7 6 5 4 3 2 1 0 W7 W6 W5 W4 W3 W2 W1 W0 Initial Value 0 0 0 0 1 1 1 1 Read Write R W R W R W R W R W R W R...

Page 151: ...h FD 15 0 in this mode In other mode except mode1 FMAR are written via decoded value from BA 16 0 of the Flash Memory address write command not the FMAR write and read directly through FMAR read FMDR...

Page 152: ...ulse ERSE Erase Start bit Erase Pulse Supply to Addressed Block Gate Bulk Pulse PGM_VFY Program Verify Read Enable Positive Gate Pump Enable ER_VFY Erase Verify Read Enable Positive Gate Pump Enable C...

Page 153: ...ble Table 12 5 Erase Sector Register Sector Sector Size Address Range Sector 0 8KB 4K word 0x00000 0x01FFF Sector 1 8KB 0x02000 0x03FFF Sector 2 24KB 0x04000 0x0BFFF Sector 3 24KB 0x0B000 0x0FFFF Sect...

Page 154: ...r ER_PWR 1 and VDD becomes below 2 9V 5 4 VEEI 1 0 These bits define VEEI Negative Gate Pump output voltage when the ER_PWR of FMCR is 1 00 9V 01 10V 10 8V 11 10V 3 2 reserved These bits are reserved...

Page 155: ...mode mode 6 is extended mode mode 7 is one chip micro controller mode This device has Internal ROM area for booting This ROM area locates in 0x00000000 when SBM Serial Boot Mode 1 i e boot mode Mode6...

Page 156: ...e mode programming control program should be prepared beforehand mode 6 7 2 Start the HMS39C7092 with a reset 3 Set UART0 input clock UCLK0 to 3 07818MHz from Source Clock 33 86MHz and start UCLK0 4 S...

Page 157: ...UART from Host Step 5 Store the flash download algorithm program into the internal SRAM Step 6 ARM branches to the start address of the flash download algorithm program Step 7 The algorithm program g...

Page 158: ...se should transferred from external memory to RAM and executed in RAM Figure 12 4 shows the execution procedure when user program mode is entered during program execution in RAM Figure 12 4 User Mode...

Page 159: ...RAM Step 5 If flash memory has been programmed Program erase control program erase flash memory in block Units before program Step 6 Program erase control program gets user application program from ho...

Page 160: ...ase should be located and executed in on chip RAM or external memory 12 6 1 Program Program Verify Mode When writing data or programs to flash memory the program flowchart shown in Figure 12 5 should...

Page 161: ...10us flash addr 0xffff FMCR 0x00 wait for 10us ptr start address ptr endaddress FMCR 0x10 wait for 10us ptr 0xffff wait for 2us ptr data ptr endaddress Trial Count 0 ptr 2 ptr 2 ptr endaddress verify...

Page 162: ...k that will be erased goes to program state so it is possible to prevent cell from being over erased after block erase When Pre program mode program address must start at first address of block to be...

Page 163: ...sh addr 0xffff FMCR 0x00 wait for 10us ptr start of block ptr end of block FMCR 0x10 wait for 10us ptr 0xffff wait for 2us ptr 0x0000 ptr end of block Trial Count 0 ptr 2 ptr 2 ptr endaddress verify i...

Page 164: ...d to ensure that every cell in the block are erased successively When Erase verify read mode verify address must start at first address of block to be erased and increase by 2 to the last address of t...

Page 165: ...MPR 0x00 wait for 20us ptr start of block FMCR 0x10 wait for 10us ptr 0xffff wait for 2us ptr 0xFFFF ptr end of block Trial Count 0 ptr 2 ptr endaddress verify is OK FMCR 0x00 wait for 2us Trial Count...

Page 166: ...emory the sequence of Figure 12 8 should be followed It is composed of pre program pre program verify erase erase verify start PrePGM Fail No Pre Program PrePGM Verify Erase Erase Verify Erase Fail Ch...

Page 167: ...FWEB rising edge FD 15 0 signals are passed into the register that FR_SEL select When value of FR_SEL 2 0 is set and FOEB is low the register s value is read through the FD 15 0 Table 12 8 shows how...

Page 168: ...7FFF Sector 7 32KB 0x28000 0x2FFFF 12 7 3 PROM Mode Operation Each flash memory operation such as program erase read are made by writing and reading the flash memory internal register Table 12 10 show...

Page 169: ...011 W 0x0002 100 W BN 011 W 0X000A RA Program Pre program verify 101 W 0x0001 011 W 0X0010 001 W RA Erase Verify read 101 W 0x0000 011 W 0x0020 001 W RA Read Address WA Write address Dout Read data Di...

Page 170: ...16 0 FC E B FOE B FR _S E L 2 0 FD 15 0 Trst Tds Td h FW E B Tw ep Don t Care Addr XX XX Xh W A Don t Care Addr XX XX Xh Tces Tpup Tpgm Tpdw 001b 011b 011b 001b Din 0005h 0000h F F F Fh Trst Tpuo Tera...

Page 171: ...2 0 1 st Cycle 2 nd Cycle RA Valid FRSTB FA 16 0 FCEB FWEB FD 15 0 FOEB Trst Tvfy Tds Tdh Tpdw Tdout Twep Tces 3 rd Cycle Read Cycle 101b 011b 001b 0001h 0010h X 000b Dout FR_SEL 2 0 RA Valid FRSTB F...

Page 172: ...D 3 3V 10 Vss 0V Vss 0V FXTVPPD 5V 10 Ta 25 C 10 Item Symbol Min Typ Max Unit CEB output delay time TCEB 70 90 ns OEB output delay time TOEB 5 10 ns Output disable delay time TOEBH 1 2 ns R_SEL output...

Page 173: ...Flash MCU HMS39C7092 A D Converter 173 Chapter 13 A D Converter...

Page 174: ...oltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin z High speed conversion Conversion time minimum 2us per channel with 8Mhz ADC...

Page 175: ...in the A D converter VREF is the A D conversion reference voltage Table 13 1 A D Converter Pins Pin Name I O Function AVDD Input Analog power supply AVSS Input Analog ground AVREF Input Analog referen...

Page 176: ...it b7 b6 b5 b4 b3 b2 b1 b0 ADCSR ADF ADST ADIE ACKS ACHS Init Val 0 0 0 0 0 0 0 0 RD WR R W R W R W R W R W R W R W R W Initial Value 0x00 ACHS Channel select Select the analog input channel 000 Analo...

Page 177: ...end of A D conversion When this signal is 1 then A D converter generates the end of conversion interrupt ADST bit indicate the start of A D conversion When this signal is 1 the A D converter start the...

Page 178: ...Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 B2 b1 b0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Reserved Init Val 0 0 0 0 0 0 0 0 0 0 000000 RD WR R R R R R R R R R R R Initial value 0x0000 bit fie...

Page 179: ...D converter operates by successive approximations with 10 bit resolution Figure 13 2 show the operation of A D converter Tca l ADCLK AIOSTO Analog fsample Output Data ADI ADS INT_AD CALEN Sn AVREF DA...

Page 180: ...verter Flash MCU HMS39C7092 180 13 4 Interrupts The A D converter generates an interrupt INT_ADC at the end of A D conversion The INT_ADC interrupt request can be enabled or disabled by the ADIE bit i...

Page 181: ...to a stable digital ground VSS at one point on the board Note on Noise To prevent damage from surges and other abnormal voltages at the analog input pins AN0 to AN4 and analog reference voltage pin V...

Page 182: ...2 AN3 AN4 Analog Input VIN GND 0 2 AVREF 0 2V C2 C5 C3 C6 R1 R2 Analog Reference Signal ACLK 7 5MHz C1 C3 10uF C4 C6 2200pF DVSS 0V DVDD 3 3V AVREF 3 3V R1 R2 1K Ceramic Capacitor Charge Capacitor FS...

Page 183: ...line it may degrade absolute accuracy The capacitor must be connected to an electrically stable ground such as AVSS If a filter circuit is used be careful of interference with digital signals on the s...

Page 184: ...r not ldr r2 r0 Check it s in the range of calibration time cmp r2 2 bne loop ldr r0 ADC_base Set the control bit in ADSR register add r0 r0 ADSR AD conversion start CKS 1 8 ADCLK ACH 0ch mov r1 0x40...

Page 185: ...Flash MCU HMS39C7092 Electrical Characteristics 185...

Page 186: ...Electrical Characteristics Flash MCU HMS39C7092 186 Chapter 14 Electrical Characteristics...

Page 187: ...C Note1 Absolute maximum continuous ratings are those values which damage to the device may occur Exposure to these conditions or conditions beyond those indicated may adversely affect device reliabil...

Page 188: ...1 39 1 82 V VDD 3 3V Output Low Voltage VOL 0 4 V VDD 3 0V IOL 0 8mA Output High Voltage VOH 2 4 V VDD 3 0V IOH 0 8mA Input current at maximum voltage II 1 mA VDD 3 0V to 3 6V Input 5 5V Table 14 4 li...

Page 189: ...arameters in Table 14 7 and bus timing parameters in Table 14 8 Table 14 6 Clock Timing Item Symbol Min Max Units Test Conditions Clock cycle time tCYC 20 1000 ns Clock pulse low width tCL 10 ns Clock...

Page 190: ...WSW1 20 Address setup time 1 tAS1 10 Read data setup time tRDS 20 Read data hold time tRDH 0 Write data delay time tWDD 20 Write data setup time 1 tWDS1 10 Write data hold time tWDH 0 Read data access...

Page 191: ...rameter Conditions Min Typ Max Units IDD Normal ADCLK 7 5MHz Input AVREF FIN 1 26KHz ramp 2 0 mA Power Down ADCLK 7 5MHz 50 uA AN Analog input voltage GND 0 2 AVREF 0 2 V Accuracy Resolution 10 bits I...

Page 192: ...re 14 1 shows the settling time of the crystal oscillator Figure 14 1 The settling time of the crystal oscillator 14 5 2 Reset Timing Figure 14 2 show the reset input timing and reset output timing Fi...

Page 193: ...Diagram of the Bus Controller Figure 14 4 The Read Timing Diagram of the Bus Controller XIN A23 to A0 nCSn nAS nRD Data read tCH tAD tCL tCYC T1 T2 tCf tCr tRDH tACC3 tAS1 tSD tPCH1 tCYC tAS1 tASD tA...

Page 194: ...2 194 Figure 14 5 Basic Bus Cycle with External Wait State Figure 14 6 Bus Release Mode Timing XIN nCSn Address nAS Data Read nHWR nLWR nRD n 1 1 Valid nWAIT T1 T2 Tw Tw Tw T3 tWTS tWTH XIN Address nB...

Page 195: ...Flash MCU HMS39C7092 Electrical Characteristics 195...

Page 196: ...Electrical Characteristics Flash MCU HMS39C7092 196...

Page 197: ...A 1 Flash MCU HMS39C7092 197 A 1 Package Dimension...

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