MagnaChip HMS39C7092, User Manual, Page: 49 / 197

Flash MCU(HMS39C7092) BUS Controller
49
16-Bit Access Areas: Figure 3.4 shows data alignment control for 16-bit access
areas. With 16-bit access areas, the lower data bus ( D
7
to D
0
) and higher data bus
( D
15
to D
8
) are used for accesses. The amount of data that can be accessed at one
time is one byte or one half-word, and a word access is executed as two half-word
accesses.
Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area)
nHWR , nLWR signals are generated according to the memory transfer width,
external memory width, A0 , and the access sequencing. The following table shows
the basic coding example assuming 16-bit external memory:
Table 3.3 Byte Lane condition by A0
CPU access Size A0 nHWR nLWR
Number of
Access
Word (32bit) X L L 2
Half-word (16-bit) X L L 1
Lower Byte (8bit) 0 H L 1
Upper Byte (8bit) 1 L H 1
Byte size
Half-word size
Word size
Lower Byte
Lower Byte
1st bus cycle Lower Byte
2nd bus cycle Lower Byte
Even Address
Odd Address Upper Byte
Upper Byte
Upper Byte
Upper Byte