MagnaChip HMS39C7092, User Manual, Page: 131 / 197

Flash MCU(HMS39C7092) UART
131
IIR Interrupt Identification Register (0x1408 ReadOnly)
b31 b8 b7 b6 b5 b4 b3 b2 b1 b0
IIR
Reserved FIFO Res Res FID IID IPEN
Reset - 00 0 0 0 00 1
Initial value : 0xXXXXXX01
IPEN 0: Interrupt Pending
1: No Interrupt pending
IID/FID Interrupt Identification Value
(refer Table 9.7)
FIFO Indicate FIFO mode
00: None-FIFO mode
11: FIFO mode
In order to provide minimum software overhead during data character transfers, the
UART prioritizes interrupts into four levels and records them in the Interrupt
Identification Register. The three levels of interrupt conditions are as follows in order
of priority:
•
Receiver Line Status
•
Received Data Ready
•
Transmitter Holding Register Empty
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the
highest priority pending interrupt to the CPU. While this CPU access occurs, the
UART records new interrupts, but does not change its current indication until the
access is complete. Table 9.6 Summary of Registers shows the contents of the IIR.
Details on each bit are :
IPEN This bit can be used in a prioritized interrupt environment to indicate
whether an interrupt is pending or not. When bit 0 is ë0í, an interrupt is
pending and the IIR contents may be used as a pointer for the appropriate
interrupt service routine. When bit 0 is ë1í, no interrupt is pending.
IID These two bits of the IIR are used to identify the highest priority interrupt
pending as indicated in Table 9.5 Interrupt control functions .
FID In the 16450 mode this bit is 0. In the FIFO mode this bit is set along with
bit 2 when a time-out interrupt is pending.
FIFO These two bits are set when FIFOEN = 1.