Operational
Overview
AES16 User Manual
46
Sample Clock Sources
The sample clock generator can derive its
reference clock from both an internal and
various external sources. Only one source can
be selected at any given time. User control of
the sample clock source selector is provided
on the Adapter page of the Lynx Mixer
application. The available clocks sources are:
On-board low-jitter oscillator (Internal)
Digital In 1- 4: word clock recovered from one of the first four AES-3 inputs
External Clock In: signal from the CLOCK IN BNC connector on the CBL-AES1604 break-out
cable
Header Clock In: signal from the board-mounted header connector
LStream Port In: word clock from an LStream device connected to the LStream header port
Phase-lock Loops and Clock Dividers
A two-stage phase-lock loop system is used to
generate a high-frequecny PLL Clock while
attenuating jitter in the selected sample clock
source. Refer to the SynchroLock section for
a description of the operation of the PLL’s.
Clock dividers derive required system clocks
from the PLL clock.
5.3 SynchroLock
™
The AES16 incorporates SynchroLock clock
synchronization technology to provide
extreme tolerance to noisy external
AES/EBU and word clock signals while
generating an ultra-low jitter clock. This
technology is especially useful for combating
noise induced on cables in complex studio
installations. SynchroLock provides clock
synchronization while insuring bit-perfect
digital transmission. When the AES16 is
connected in an AES/EBU daisy chain,
SynchroLock acts like a jitter firewall to
prevent the propagation of jitter to
downstream devices.
By coupling statistical analysis with low-noise
clock generation techniques, SynchroLock is
capable of attenuating jitter on incoming
AES/EBU signals by a factor of 3000:1.
Compare this to attenuation of 100:1 or less
for professional quality analog phase-lock
loops (PLL). SynchroLock can easily handle
AES/EBU signals with jitter levels in excess
of 800 nanoseconds.
The SynchroLock sample clock is a two-stage
system that is comprised of a fast-locking
analog PLL and digitally controlled crystal-
based secondary stage. Due to extensive
number crunching of the secondary stage,
SynchroLock typically requires one to two
minutes to achieve final lock. While the
secondary stage is working, the fast-locking
PLL loop maintains lock, but with much less
jitter attenuation than the secondary stage.
When the final lock state is achieved, the
secondary stage is switched on line and
becomes the system clock source. In some
cases this switching process may cause a
momentary disruption in digital I/O. Because
of this, it is recommended that recording or
playback not be started until the green LOCK
