SDC-SSD30AG
Hardware Integration Guide, version 3.3
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11
Laird Technologies
SDIO Interface Timing
SDIO Timing Definitions
Parameter
Description
Min Max Unit
SDIO CLK (All values are referred to minimum VIH and maximum VIL
b
f
PP
Clock frequency data transfer mode
0
25
MHz
t
WL
Clock low time
10
-
ns
t
WH
Clock high time
10
-
ns
t
TLH
Clock rise time
-
10
ns
t
THL
Clock fall time
-
10
ns
Inputs: CMD, Data (referenced to CLK)
t
ISU
Input setup time
5
-
ns
t
IH
Input hold time
5
-
ns
Outputs: CMD, Data (referenced to CLK)
t
O_DLY (min)
Output delay time during data transfer mode
0
14
ns
t
O_DLY (max)
Output delay time during data transfer mode
0
50
ns
a)
Timing is based on CL
≤
40pF load on CMD and Data
b)
Min (Vih) = 0.7 x VDDIO and max (Vil) = 0.2 x VDDIO
