SDC-SSD30AG
Hardware Integration Guide, version 3.3
Americas: +1-800-492-2320 Option 2
Europe: +44-1628-858-940
Hong Kong: +852-2268-6567 x026
2
Laird Technologies
R
EVISION
H
ISTORY
Version
Revision Date
Change Description
1.0
11/19/09
Transitioned Application Notes documentation to Hardware
Integration Guide format.
1.01
11/23/09
Updated Specifications table.
1.02
12/15/09
Updated Power Consumption values in the Specifications
table.
1.03
01/10/10
Revised Operational Description. Added Regulatory section.
Revised pinouts.
Added RF Layout Guidelines section.
1.04
04/16/10
Revised pinouts and certification information. Added
schematic.
1.05
04/26/10
Revised Required Documentation section. Revised pin
definitions. Revised DC Electrical Characteristics table. Revised
Power Sequence Operations information. Removed
schematic.
1.06
05/04/10
Added I/O signal details.
1.07
05/27/10
Updated images; added SDIO Interface Timing information;
revised pin definitions
1.08
08/24/10
Updated block diagram.
1.09
12/28/10
Revised mechanical drawings.
1.10
01/12/11
Revised Pinout table.
2.0
04/05/11
Corrections to BT pin descriptions on Pinout table.
2.1
04/15/11
Revised Block Diagram.
2.2
07/14/11
Added PCB footprint drawing.
2.3
08/09/11
Revised Mechanical drawings.
2.4
05/17/12
Added Appendix A: Schematic
Added SSD30AG/SSD40NBT Pin Comparison table.
3.0
08/03/12
Updated Certifications.
3.1
09/10/12
Updated the following Pin descriptions: WLAN_ACTIVE (49),
BT_ACTIVE (52).
3.2
1/31/13
Updated 5 GHz Frequencies and Operating Channels
3.3
20 March 2014
Add note regarding the following pins: CHIP_PWD_L,
SYS_RST_L, BT_RST_L, VDDIO_DR
