Laird SDC-SSD30AG, Hardware Integration Manual

Page: 10 / 26

SDC-SSD30AG
Hardware Integration Guide, version 3.3
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10
Laird Technologies
DC E
LECTRICAL
C
HARACTERISTICS
Note: VDDIO is the reference voltage for all chip IO and applies to the following pins: SDIO_DATA_0,
SDIO_DATA_1, SDIO_DATA_2, SDIO_DATA_3, SDIO_CLK, SDIO_CMD, CHIP_PWD_L,
SYS_RST_L, WL_LED_ACT, EX_GPIO, WLAN_ACTIVE, BT_ACTIVE, BT_PRIORITY, BT_FREQ,
MODE_SEL
Symbol Parameter Min Typ Max Unit
VCC DC Supply Voltage 3.0 3.3 3.6 V
I
VCC
DC Supply Current,
(max transmit power setting)
802.11a
Transmit: 380 mA (1254 mW)
Receive: 115 mA ( 380 mW)
Standby: 3 mA ( 10 mW)
802.11b/g
Transmit: 325 mA (1072 mW)
Receive: 95 mA ( 314 mW)
Standby: 2 mA ( 7 mW)
mA
VDDIO Digital I/O Reference Voltage 1.71 1.8 3.46 V
I
VDDIO
Digital I/O Current 0.05 0.40 mA
V
IH
High Level Input Voltage 0.8 x V
DDIO
- V
DD
+ 0.3 V
V
IL
Low Level Input Voltage –0.3 - 0.2 x V
DDIO
V
V
OH
High Level Output Voltage
V
DDIO
–
0.35
- - V
V
OL
Low Level Output Voltage - - 0.40 V
C
IN
Input Capacitance - 6 - pF
The SSD30AG has an internal pull-down on CHIP_PWD_L, so when the host pulls it high, the pad sinks
current. The amount of current depends on VDDIO. ~10µA for VDDIO = 1.8V and ~40µA when VDDIO =
3.3V. As a result, the solution power consumption is at least 18-132µW higher than the chip power
consumption in non-CHIP_PWD states.
The analog power-on reset circuit in the SSD30AG is also optimizer for VDDIO = 1.8V, thus the chip draws an
extra 3.5µA when VDDIO = 3.3V. The SSD30AG has an internal pull-up on SYS_RST_L, thus to minimize
CHIP_PWD power consumption, customer designs should not tie CHIP_PWD_L and SYS_RST_L together.