SDC-SSD30AG
Hardware Integration Guide, version 3.3
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5
Laird Technologies
B
LOCK
D
IAGRAM
The block diagram for the SDC-SSD30 with Atheros AR6002 is as follows:
S
PECIFICATIONS
Feature
Description
System Interface
1-bit or 4-bit Secure Digital I/O
Physical Interface
0.4 mm pitch QFN (Quad Flat No leads)
Antenna Interface
Pads for 2 dual-band antennas
Chip Set
Atheros AR6002
Input Voltage Requirements
3.3 VDC ± 10% (core)
I/O Signaling Voltage
1.8 or 3.3 VDC ± 10%
Current Consumption
(At maximum transmit power setting)
802.11a
Transmit: 380 mA (1254 mW)
Receive: 115 mA ( 380 mW)
Standby: 3 mA ( 10 mW)
802.11b/g
Transmit: 325 mA (1072 mW)
Receive: 95 mA ( 314 mW)
Standby: 2 mA ( 7 mW)
Operating Temperature
-30° to 70°C (-22° to 158°F)
Operating Humidity
10 to 90% (non-condensing)
Storage Temperature
-30° to 85°C (-22° to 185°F)
Storage Humidity
10 to 90% (non-condensing)
Maximum Electrostatic Discharge
4 kV
Length
15.0 mm (0.59”)
Width
15.0 mm (0.59”)
Thickness
2.6 mm (0.1”)
Weight
1.0 g (0.04 oz.)
Mounting
See the “
Mounting
” section for more information.
Wi-Fi Wireless Media
Direct Sequence-Spread Spectrum (DSSS)
Orthogonal Frequency Divisional Multiplexing (OFDM)
