COMPONENT MAINTENANCE MANUAL
AVIATION RECORDERS
FA2100CVR
Rev. 15 Page 40
Apr. 14/16
Description and Operation
23–70–04
Use or disclosure of information on this sheet is subject
to the restrictions on the cover page of this document.
(4)
Discrete Data Interface
The Discrete Data Interface includes Aircraft Interface output signals:
RECORD L, TEST L, VOICE ERASE L, STOP L, and PREAMP PWR FAIL L.
Each output signal is 0 – 5 V, with a 10–kohm pull–up resistor on an open col-
lector output. The Discrete Data Interface Audio Compressor output signals
are CVR FAULT L and TEST GOOD L.
(5)
Audio Monitor Interface
An audio output channel for test monitoring provides a combination of six repro-
cessed Adaptive Differential Pulse Code Modulations (ADPCM) data channels,
with or without a 640 Hz test tone, or a 400 Hz tone indicating bulk erase to a
listener. The output level is 2.55 Vrms into a 622–ohm load with respect to any
input reference level. An audio return ground is included in this interface.
(6)
Audio Compressor/Acquisition Processor Interface
The AC/AP Interface includes the following signals:
(a)
Serial TDM Bus signals TCLK, TFRM, TADD, and TDAT
(b)
Master Clock Input F8.192 MHz
(c)
Master Reset AC RESET L
(d)
BIT Control Input TEST MODE L
(e)
Power/Ground Signals V5N, V5P, and GND
The TCLK and TFRM signals are generated by the Acquisition Processor and
provide bit and TDM frame synchronization, respectively. TADD and TDAT are
bidirectional signals; receiver specific port identification is furnished by TADD
bits [7...0], and the data associated with the targeted receiver occur as TDAT
bits [15...0].
D.
Acquisition Processor (AP) PWA
The Acquisition Processor PWA performs data management of audio data as a
Cockpit Voice Recorder (CVR). It also provides various command and control func-
tions for the recorder, as well as power management.
The Acquisition Processor PWA actually consists of two separate processors: the
Store Manager Processor (SMP) and the Flight Data Processor (FDP). However, in
the FA2100 CVR configuration the SMP is the only processor functioning, with the
exception of p/n: 205E2502
−
14 since the Data Link signals utilize the FDP proces-
The document reference is online, please check the correspondence between the online documentation and the printed version.
