AD-130GE
16
7. Inputs and outputs interface
7.1. Overview
All input and output signals pass through the GPIO (General Purpose Input and Output) module.
The GPIO module consists of a Look-Up Table (LUT – Cross-Point Switch), 2 Pulse Generators
and a 12-bit counter. In the LUT, the relationship between inputs, counters and outputs is
governed by internal register set-up.
Fig. 9 Cross point switch
7.1.1 LUT (Cross Point Switch)
The LUT works as a cross-point switch which allows connecting inputs and outputs freely. The
signals LVAL_IN, DVAL_IN, FVAL_IN and EEN_IN all originate from the camera timing circuit.
On this diagram, Trigger 0 is used for exposure and Trigger 1 is used for Delayed Readout. The
Time Stamp Reset signal can reset the time stamp specified in GigE Vision Format. This signal
can be used when time stamps from several cameras connected are coincident with each other.
FVA L2
LVA L2
D VA L2
E xposure A ctive2
C ross Point sw itch
O ptical In 1
O ptical In 2
S oftware Trigger 0
S oftware T rigger 3 / A ction 2
F ram e Start Trigger
Tim e S tam p R eset
S oftware T rigger 2 / A ction 1
S oftware Trigger 1
S equence Table R eset
T TL In 1
LVD S In
FVA L1
LVA L1
D VA L1
E xposure A ctive1
T TL In 2
C lear S ource 0
P ulse G enerator 0 O ut
O ptical O ut 1
O ptical O ut 2
(12bit C ounter)
P ulse
G enerator
C lock (M H z)
(P ixel C lock
51.324 M H z
）
T TL O ut 1
(20bit C ounter)
P ulse G enerator 0
S oftware Trigger 0
S oftware Trigger 3 / A ction 2
S oftware Trigger 2 / A ction 1
S oftware Trigger 1
C am era 0
(Interface#1)
C am era 1
(Interface#2)
Transfer S tart T rigger
Fram e Start T rigger
Transfer S tart T rigger
C am era 0
C am era 1
S equence Table R eset
C am era 0
C am era 1
C lear S ource 1
C lear S ource 2
C lear S ource 3
P ulse G enerator
(20bit C ounter)
P ulse G enerator 1
(20bit C ounter)
P ulse G enerator 2
(20bit C ounter)
P ulse G enerator
C lock P re-scaler
P ulse G enerator 1 O ut
P ulse G enerator 2 O ut
P ulse G enerator 3 O ut
3
