Intel Pentium III, Design Manual

Page: 67 / 68

Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 8-5
SLEWCTRL 110
Ω
1% pull-down to GND.
VID[3:0]
Connect to on-board VR or VRM. For on-board VR, a 1 K
Ω
pull-up to 3.3V is
required. Some of these solutions have internal pull-ups. Optional override
(jumpers, ASIC, etc) could be used. May also connect to system monitoring
device.
VID25
Connect to on-board VR or VRM. 25mV should connect to VID5 or VID25mV. For
on-board VR, a 1 K
Ω
pull-up to 3.3V is required. Some of these solutions have
internal pull-ups. Optional override (jumpers, ASIC, etc) could be used. May also
connect to system monitoring device.
Table 8-6. Power Signals
CPU Pin Pin Connection
DYN_OE Connected to V
TT
through a 1 K
Ω
pullup resistor
PLL1, PLL2
Low pass filter on VCC
CORE
provided on MB. Typically a 4.7 µH inductor in series
with VCC
CORE
is connected to PLL1 then through a series 22-100µF capacitor to
PLL2.
Vcc
CMOS1.5
Connected to the Vcc1.5 power supply. Must have some high and low frequency
decoupling.
Vcc
CMOS2.5
Connected to 2.5 V voltage source. Should have some high and low frequency
decoupling.
Vcc
CMOS1.8
Connected to 1.8V voltage source. Should have some high and low frequency
decoupling.
VCC
CORE
Connect to core voltage regulator. Provide low frequency decoupling.
Guidelines: 16 4.7µF in 1206 package placed inside PGA370 socket cavity on
primary side of board.
VREF[7:0]
Connect to Vref voltage divider made up of 75
Ω
1% and 150
Ω
1% resistors
connected to V
TT
. Processor VREF must be separate from Chipset VREF.
Guidelines: Three each (minimum) 0.1 µF in 0603 package placed within 500
mils of VREF pins.
VCMOS_REF Connect to 1.0 V voltage divider derived from VccCMOS.
VTT_ PWRGD
Connected to V
TT
through a 1 K
Ω
pullup resistor, and connect to VTT_PWRGD
circuitry.
VTT
Connect AG1, AK16, AL13, AL21, AN11, AN15, G35, G37, AD36, AB36, X34,
AA33, AA35, AN21, E23, S33, S37, U35, U37, AH20 to 1.25 V regulator. Provide
high and low frequency decoupling.
Guidelines: 20 0.1 µF in 0603 package placed within 200 mils of each PGA 370
socket; place as many as possible inside socket cavity.
Reserved
The following pins must be left as no-connects: AK30, AL1, E21, F10, L33, N33,
N35, Q33, Q35, Q37, R2, W35, X2, Y1, Z36.
Table 8-5. Miscellaneous Signals
CPU Pin Pin Connection