5-8
Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
5.5.2
Processor PLL Filter Recommendations
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements. A low
pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated, decoupled
power source for the internal PLL.
5.5.2.1
Topology
PGA370 processors have internal phase lock look (PLL) clock generators, which are analog and require
a quiet power supply to minimize jitter. PLL1 should have a 4.7-µH inductor connected in series to
Vcc
CORE
, and PLL2 should be connected through a capacitor (22- to 100-µF) to PLL1. See
Figure 5-7
.
Other routing requirements:
•
The capacitor (C) should be close to the PLL1 and PLL2 pins, < 0.1
Ω
per route.
•
The PLL2 route should be parallel and next to PLL1 route (minimize loop area).
•
The inductor (L) should be close to C; any routing resistance should be inserted between Vcc
CORE
and L.
5.5.2.2
Filter Specification
The function of the filter is to protect the PLL from external noise through low-pass attenuation.
The low-pass specification, with input at Vcc
CORE
and output measured across the capacitor, is as
follows:
•
< 0.2dB gain in pass band
•
< 0.5dB attenuation in pass band (see DC drop in next set of requirements)
•
> 34dB attenuation from 1MHz to 66MHz
•
> 28dB attenuation from 66MHz to core frequency
Figure 5-7. Processor PLL Filter
4.7
µµµµ
H
22-100
µµµµ
F
PLL2
PLL1
PLL
Processor
VCC_CORE
