6-2
Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
The example workaround circuit, shown in
Figure 6-1
, requires circuit modifications for ITP tools to
function correctly. These modifications must remove the workaround circuitry from the platform and may
cause systems to fail to boot. Issuing the ITP 'Reset Target' command on failing systems will reset the
system while providing a sufficient rising edge on the TCK pin to ensure system boot.
The example workaround circuit shown does not support production motherboard test methodologies
that require the use of the processor JTAG/TAP port. Alternative workaround solutions must be found if
such test capability is required.
NOTES:
1. For Production Boards: Depopulate R5
2. To use ITP: Install R5, Depopulate R4
3. Assumes the inputs to the CPU_PWRGD are open collector signals that are Wire-ANDed together
The example workaround circuit assumes that the PWRGD inputs into the processors are open collector.
Tying the PWRGD inputs together in a Wired-AND fashion allows each processor to receive PWRGD at
the same time but at the latter of the 2 separate PWRGD assertions. If separation of the PWRGD inputs
to each processor is required, extra circuitry will be required.
Please consult the Pentium
®
III Processor Specification Update for additional information on this issue.
Figure 6-1. Example Dual Processor THERMTRIP# Workaround Circuit
TCK
PWRGD
39 ohm
R5
R1
R2
R3
R4
0 ohm
330 ohm
150 ohm
680 ohm
CPU1
ITP
2.5V
TCK
PWRGD
CPU2
TCK
