5-6
Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
5.4.2.2
Location of Bulk Decoupling
The location of bulk capacitance is not as critical as the high frequency decoupling components.
However careful placement is still important for these components to minimize the effects of parasitic
board impedances impacting transient response capability. Further, location and component
impedances are useful in simulation of the power conversion circuit. Bulk components should typically
be placed close to the processor sockets to minimize AC delays.
It should be further noted that bulk capacitors on VRMs are effectively electrically located behind the
inductance of the converter pins. As a result bulk capacitors need to be utilized close to the processor
socket.
The recommended number of bulk decoupling components and board load model for use with VRMs is
illustrated in
Table 5-1
and
Figure 5-4
.
5.5
Recommendations
Intel recommends using simulation to design and verify Intel
®
Pentium
®
III Processor with 512KB L2
Cache dual processor based systems. With the estimates provided in the previous section, a model of
the power source, and the model of the processor, system developers can begin analog modeling. The
following sections contain Intel's design recommendations.
Table 5-1. Bulk Capacitance Recommendations
Design Type
Bulk Capacitance
ESR
ESL
RMS Current Rating
On-board design
4 OSCON, 560
µ
F
12m
Ω
3.1 nH max
5.04 A
rms
