3-8
Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
3.7.4
Minimizing Crosstalk
The following general rules will minimize the impact of crosstalk in the high speed AGTL bus design:
•
Maximize the space between traces. Maintain a minimum of 10 mils (assuming a 5 mil trace)
between trace edges wherever possible. It may be necessary to use tighter spacing when routing
between component pins. When traces have to be close and parallel to each other, minimize the
distance that they are close together, and maximize the distance between the sections when the
spacing restrictions relaxes.
•
Avoid parallelism between signals on adjacent layers if there is no AC reference plane between
them. As a rule of thumb, route adjacent layers orthogonally.
•
Since AGTL is a low signal swing technology, it is important to isolate AGTL signals from other
signals by at least 25 mils. This will avoid coupling from signals that have larger voltage swings, such
as 3.3 V system memory.
•
Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the nominal
characteristic impedance within the AGTL specification. This can be done by minimizing the height of
the trace from its reference plane, which minimizes the crosstalk.
•
Route AGTL address, data and control signals in separate groups to minimize crosstalk between
groups. Keep at least 25 mils between each group of signals.
•
Minimize the dielectric used in the system. This makes the traces closer to their reference plane and
thus reduces the crosstalk magnitude.
•
Minimize the dielectric process variation used in the PCB fabrication.
•
Minimize the cross sectional area of the traces. This can be done by narrower traces and/or by using
thinner copper, but the trade-off for this smaller cross sectional area is a higher trace resistivity that
can reduce the falling edge noise margin because of the I*R loss along the trace.
3.8
Layout Rules for Non-AGTL (CMOS) Signals
The following layout rules should be used for all CMOS signals:
•
The trace impedance should be 60
Ω
+/- 15%.
•
External termination resistors should be placed in the middle of the trace to prevent long reflection
times and reduce reflection ledges.
•
Do not route CMOS traces next to AGTL traces. Switching noise on the AGTL traces may attack the
nearby CMOS traces.
•
Route a CMOS trace on one signal layer. If layer switching is unavoidable, try minimize the number
of layer switches.
•
Try to use only one reference plane for a trace (either Vcc or Vss).
•
Although CMOS signals are slow, they may still have speed path problems. This is especially true for
APIC clock and APIC data. Try to avoid long routes.
