Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
3-11
3.10.1.1.2
JTAG Signal Layout Guidelines
Reflections on TCK that cause mid-threshold ringing will render the primary system debug tool
inoperative. Simulate the behavioral model, and verify signal integrity using your system bus signal
analysis tools. The following table provides the JTAG signal layout guidelines. It is highly recommended
that TCK be simulated to ensure proper signal quality is maintained.
3.10.1.1.3
Execution Signal Layout Guidelines
Table 3-11. JTAG Signal Layout Guidelines
Signal
Routing Notes
Sample Layout
TCK
Critical JTAG signals which requires timing and signal
integrity considerations, driver is 74VCX16245 with
external edge rate control on TCK
Figure 3-5
TMS, TDI, TDO
Critical JTAG signal which requires timing and signal
integrity considerations. ITP driver is 74VCX16245.
TMS must be routed with TCK.
Figure 3-4
a
TRST#
On target resistors should be used to force TRST#
assertion (low).
Figure 3-4
b
Figure 3-5. TCK Termination, DP System
Table 3-12. Execution Signals Routing Guidelines
Signal
Routing Notes
Sample Layout
PREQx#
AGTL signal routing guidelines apply
Figure 3-4
a
PRDYx#
Figure 3-6
RESET#
The flight time of the RESET# signal from the closest
processor must be added to the arrival time of BCLK at
the Debug Port.
Figure 3-7
Figure 3. TCK Termination, DP System
