Intel M70KLP Series, Service Manual

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Intel® Server System M70KLP Family Service Guide
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DDR4 DRAM DIMM Population Rules
The following DDR4 SDRAM population rules apply for most reliable operation.
• Mixed DDR4 DIMM rules:
Note: Intel will only support mixed DDR4 DRAM DIMM configurations as defined in the Intel DDR4
Support Disclaimer above.
o
Mixing DDR4 DIMMs of different speeds and latencies is not supported within or across
processors. If a mixed configuration is encountered, the BIOS attempts to operate at the highest
common speed and the lowest latency possible.
o
x4 and x8 DDR4 DIMMs may be mixed in the same channel.
o
Mixing of DDR4 DIMM types (RDIMM, LRDIMM, 3DS-RDIMM, 3DS-LRDIMM) within or across
processors is not supported. This is a Fatal Error Halt in Memory Initialization.
• For a single DDR4 DIMM in a dual-slot channel, populate slot 0 (white slot).
Chan 5 Chan4 Chan 3
IM
C
1
CPU
IM
C
0
Chan 0 Chan 1 Chan 2
Slot
0
Slot
1
Slot
0
Slot
1
Slot
0
Slot
1
Slot
1
Slot
0
Slot
1
Slot
0
Slot
1
Slot
0
DDR4 DDR4 DDR4 DDR4 DDR4 DDR4
• For multiple DDR4 DIMMs per channel:
o
For RDIMM, LRDIMM, 3DS-RDIMM, and 3DS-LRDIMM, always populate DIMMs with higher
electrical loading in slot 0 (white slot).
o
When populating a quad-rank DDR4 DIMM with a single- or dual-rank DDR4 DIMM in the same
channel, the quad-rank DDR4 DIMM must be populated farthest from the processor. Incorrect
DIMM placement results in an MRC error code. A maximum of 8 logical ranks can be used on any
one channel, as well as a maximum of 10 physical ranks loaded on a channel.
• Memory slots associated with a given processor socket cannot be used if no processor is installed
within the socket.
• Processor sockets are self-contained and autonomous. However, all memory subsystem support
(such as memory RAS and error management) in the BIOS Setup are applied commonly for each
installed processor.
• For best system performance, memory must be installed in all six channels for each installed
processor.
• For best performance, when NOT populating all memory channels, DDR4 DIMMs must be populated
symmetrically between IMCs into memory slots on both sides of the CPU for each installed CPU
o
Example: when populating 4 DDR4 DIMMs to a given CPU, the DIMMs must be installed to
memory channels 0, 1, 3, and 4 as shown below.
Chan 5 Chan4 Chan 3
IMC
1
CPU
IM
C
0
Chan 0 Chan 1 Chan 2
Slot
0
Slot
1
Slot
0
Slot
1
Slot
0
Slot
1
Slot
1
Slot
0
Slot
1
Slot
0
Slot
1
Slot
0
DDR4 DDR4 DDR4 DDR4
• For best system performance in a multi-processor configuration, the installed DDR4 DIMM population
must be the same for each installed processor.