Intel E5420 - CPU XEON QUAD CORE 2.50GHZ FSB1333MHZ 12M LGA771 HALOGEN FREE TRAY Datasheet Download Page 74

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Signal Definitions

DEFER#

DEFER# is asserted by an agent to indicate that a transaction cannot

be guaranteed in-order completion. Assertion of DEFER# is normally

the responsibility of the addressed memory or I/O agent. This signal

must connect the appropriate pins of all processor FSB agents.

DP[3:0]#

I/O

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]#

signals. They are driven by the agent responsible for driving

D[63:0]#, and must connect the appropriate pins of all processor

FSB agents.

DRDY#

I/O

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be deasserted to insert idle clocks.

This signal must connect the appropriate pins of all processor FSB

agents.

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

FERR#/PBE#

FERR#/PBE# (floating-point error/pending break event) is a

multiplexed signal and its meaning is qualified by STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating-point

error and will be asserted when the processor detects an unmasked

floating-point error. When STPCLK# is not asserted, FERR#/PBE# is

similar to the ERROR# signal on the Intel387 coprocessor, and is

included for compatibility with systems using MS-DOS*-type floating-

point error reporting. When STPCLK# is asserted, an assertion of

FERR#/PBE# indicates that the processor has a pending break event

waiting for service. The assertion of FERR#/PBE# indicates that the

processor should be returned to the Normal state. For additional

information on the pending break event functionality, including the

identification of support of the feature and enable/disable

information, refer to Vol. 3 of the Intel

64 and IA-32 Architectures

Software Developer’s Manual and the Intel Processor Identification

and the CPUID Instruction application note.

FORCEPR#

The FORCEPR# (force power reduction) input can be used by the

platform to cause the Quad-Core Intel® Xeon® Processor 5400

Series to activate the Thermal Control Circuit (TCC).

GTLREF_ADD_MID
GTLREF_ADD_END

GTLREF_ADD determines the signal reference level for AGTL+

address and common clock input lands. GTLREF_ADD is used by the

AGTL+ receivers to determine if a signal is a logical 0 or a logical 1.

Please refer to

Table 2-19

and the appropriate platform design

guidelines for additional details.

Table 5-1.

Signal Definitions (Sheet 4 of 8)

Name

Type

Description

Notes

Signals

Associated Strobes

D[15:0]#, DBI0#

DSTBN0#

D[31:16]#, DBI1#

DSTBN1#

D[47:32]#, DBI2#

DSTBN2#

D[63:48]#, DBI3#

DSTBN3#

Signals

Associated Strobes

D[15:0]#, DBI0#

DSTBP0#

D[31:16]#, DBI1#

DSTBP1#

D[47:32]#, DBI2#

DSTBP2#

D[63:48]#, DBI3#

DSTBP3#

Summary of Contents for E5420 - CPU XEON QUAD CORE 2.50GHZ FSB1333MHZ 12M LGA771 HALOGEN FREE TRAY

Page 1: ...318589 005 Quad Core Intel Xeon Processor 5400 Series Datasheet August 2008 ...

Page 2: ...ch may cause the product to deviate from published specifications Current characterized errata are available on request 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Processors will not operate including 32 bit operation without an Intel 64 architecture enabled BIOS ...

Page 3: ...0 1 DC Characteristics 24 2 10 2 Input Device Hysteresis 25 2 11 Mixing Processors 26 2 12 Absolute Maximum and Minimum Ratings 26 2 13 Processor DC Specifications 27 2 13 1 Flexible Motherboard Guidelines FMB 27 2 13 2 VCC Overshoot Specification 38 2 13 3 Die Voltage Validation 39 2 14 AGTL FSB Specifications 39 3 Mechanical Specifications 43 3 1 Package Mechanical Drawings 43 3 2 Processor Comp...

Page 4: ...p Grant Snoop State 101 7 3 Enhanced Intel SpeedStep Technology 101 8 Boxed Processor Specifications 103 8 1 Introduction 103 8 2 Mechanical Specifications 105 8 2 1 Boxed Processor Heat Sink Dimensions CEK 105 8 2 2 Boxed Processor Heat Sink Weight 113 8 2 3 Boxed Processor Retention Mechanism and Heat Sink Support CEK 113 8 3 Electrical Requirements 113 8 3 1 Fan Power Supply Active CEK 113 8 3 ...

Page 5: ...ries Package Drawing Sheet 3 of 3 46 3 5 Processor Top side Markings Example 49 3 6 Processor Land Coordinates Top View 49 3 7 Processor Land Coordinates Bottom View 50 6 1 Quad Core Intel Xeon Processor X5492 and X5482 C step Thermal Profile 81 6 2 Quad Core Intel Xeon Processor X5400 Series Thermal Profiles A and B 83 6 3 Quad Core Intel Xeon Processor E5400 Series Thermal Profile 86 6 4 Quad Co...

Page 6: ...ns 40 3 1 Package Loading Specifications 47 3 2 Package Handling Guidelines 48 3 3 Processor Materials 48 4 1 Land Listing by Land Name 51 4 2 Land Listing by Land Number 61 5 1 Signal Definitions 71 6 1 Quad Core Intel Xeon Processor X5492 and X5482 C step Thermal Specifications 81 6 2 Quad Core Intel Xeon Processor X5492 and X5482 C step Thermal Profile Table 82 6 3 Quad Core Intel Xeon Processo...

Page 7: ...March 2008 003 Added product information for the Quad Core Intel Xeon Processor L5400 Series April 2008 004 Corrected L1 cache size Introduced X5492 Updated X5482 power levels on E step August 2008 005 Maintains change bars from version 004 Denoted in the Introduction section that E step of the X5482 falls into the 120W X5400 family Added X5492 processor to Table 7 1 and in Introduction section Au...

Page 8: ...8 Quad Core Intel Xeon Processor 5400 Series Datasheet ...

Page 9: ...gy provides power management capabilities to servers and workstations Quad Core Intel Xeon Processor 5400 Series features include Intel Wide Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 1 SSE4 1 Advanced Dynamic Execution improves speculative execution and branch prediction internal...

Page 10: ...ction 2 13 1 Refer to the appropriate platform design guidelines for implementation details The Quad Core Intel Xeon Processor 5400 Series supports either 1066 MHz 1333 MHz or 1600 MHz Front Side Bus operations The FSB utilizes a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus c...

Page 11: ... Xeon Processor E5400 Series A mainstream performance version of the Quad Core Intel Xeon Processor X5400 Series For this document Quad Core Intel Xeon Processor E5400 Series is used to call out specifications that are unique to the Quad Core Intel Xeon Processor E5400 Series SKU Quad Core Intel Xeon Processor L5400 Series Intel 64 bit microprocessor intended for dual processor server blades and e...

Page 12: ...dled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric a...

Page 13: ...eloper intel com Document Document Number1 Notes AP 485 Intel Processor Identification and the CPUID Instruction 241618 2 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Intel 64 and IA 32 Architectures Software Developer s Manual Volum...

Page 14: ...14 ...

Page 15: ..._MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA_MID and GTLREF_DATA_END is used for the 4X front side bus signaling group and GTLREF_ADD_MID and GTLREF_ADD_END is used for the 2X and common clock front side bus signaling groups GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END ...

Page 16: ...component For further information and guidelines refer to the appropriate platform design guidelines 2 3 1 VCC Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must assure a low interconnect resistance from the regulator EVRD or VRM pins to the LGA771 socket Bulk decoupling must be provided on the baseboard to...

Page 17: ...ng signal integrity requirements as outlined in Table 2 20 The Quad Core Intel Xeon Processor 5400 Series utilizes differential clocks Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core frequencies Notes 1 Individual processors operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequenc...

Page 18: ... frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The Quad Core Intel Xeon Processor 5400 Series uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 3 sp...

Page 19: ...voltage Transitions above the specified VID are not permitted Table 2 12 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 13 and Table 2 2 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 12 and Table 2 14 Refer to...

Page 20: ...1 1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 1 1 0 0 1 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 1 1 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0 1 0 1 1 0 1 3375 68 1 1 0 1 0 0 0 9625 2A 0 1 0 1 0 ...

Page 21: ...ate platform design guidelines For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors RTT For details see Table 2 19 TAP CMOS Asynchronous inputs and CMOS Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnecte...

Page 22: ...timings are specified with respect to rising edge of BCLK0 ADS HIT HITM and so forth and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLK0 Asynchronous signals are still present A20M IGNNE and so forth and can become active at any time during the clock cycle Table 2 6 identifies which signals ar...

Page 23: ...SE VSS_DIE_SENSE2 VSS VTT VTT_OUT VTT_SEL Table 2 6 FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals1 Table 2 7 AGTL Signal Description Table AGTL signals with RTT AGTL signals with no RTT A 37 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR REQ 4 0 RS 2 0 RSP TRDY BPM 5 0 BPMb 3 0 RESET BR 1 0 Table 2 8 Non AGTL Signal De...

Page 24: ...f each signal may be required with each driving a different voltage level 2 10 Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary one wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The Quad Core Intel Xeon Processor 5400 Series contains Digital Thermal Sensor DTS s...

Page 25: ...2 10 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range 0 150 VTT V Vhysteresis Hysteresis 0 1 VTT N A V Vn Negative edge threshold voltage 0 275 VTT 0 500 VTT V Vp Positive edge threshold voltage 0 550 VTT 0 725 VTT V Isource High level output source VOH 0 75 VTT 6 0 N A mA Isink Low level output sink VOL 0 25 VTT 0 5 1 0 mA Ileak High impedanc...

Page 26: ...12 Absolute Maximum and Minimum Ratings Table 2 11 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term r...

Page 27: ... same information is presented graphically in Figure 2 8 and Figure 2 4 The FSB clock signal group is detailed in Table 2 20 BSEL 2 0 and VID 6 1 signals are specified in Table 2 15 The DC specifications for the AGTL signals are listed in Table 2 16 Legacy signals and Test Access Port TAP signals follow DC specifications similar to GTL The DC specifications for the PWRGOOD input and TAP signal gro...

Page 28: ...h FMB 150 A 4 5 6 9 18 ICC ICC for Quad Core Intel Xeon Processor X5400 Series with multiple VID Launch FMB 125 A 4 5 6 9 ICC ICC for Quad Core Intel Xeon Processor E5400 Series with multiple VID Launch FMB 102 A 4 5 6 9 ICC ICC for Quad Core Intel Xeon Processor L5400 Series with multiple VID Launch FMB 60 A 4 5 6 9 ICC ICC for Quad Core Intel Xeon Processor L5408 with multiple VID Launch FMB 48 ...

Page 29: ...ad Core Intel Xeon Processor L5400 Series Launch FMB 50 A 6 14 ICC_TDC Thermal Design Current TDC Quad Core Intel Xeon Processor L5408 Launch FMB 40 A 6 14 ICC_VTT_OUT DC current that may be drawn from VTT_OUT per land 580 mA 16 ICC_GTLREF ICC for GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END 200 µA 7 ICC_VCCPLL ICC for PLL supply 260 mA 12 ITCC ICC for Quad Core Intel Xeon Pro...

Page 30: ...ividual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings 12 This specification applies to the VCCPLL land 13 Baseboard bandwidth is limited to 20 MHz 14 ICC_TDC is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature as...

Page 31: ...r thermal protection circuitry should not trip for load currents greater than ICC_TDC 2 Not 100 tested Specified by design characterization Figure 2 3 Quad Core Intel Xeon Processor X5400 Series Load Current versus Time 10 0 10 5 110 115 12 0 12 5 13 0 0 0 1 0 1 1 10 10 0 10 0 0 Time Duration s Sustained Current A Figure 2 4 Quad Core Intel Xeon Processor E5400 Series Load Current versus Time 75 8...

Page 32: ...ID 0 023 VID 0 033 1 2 3 15 VID 0 019 VID 0 029 VID 0 039 1 2 3 20 VID 0 025 VID 0 035 VID 0 045 1 2 3 25 VID 0 031 VID 0 041 VID 0 051 1 2 3 30 VID 0 038 VID 0 048 VID 0 058 1 2 3 35 VID 0 044 VID 0 054 VID 0 064 1 2 3 40 VID 0 050 VID 0 060 VID 0 070 1 2 3 45 VID 0 056 VID 0 066 VID 0 076 1 2 3 50 VID 0 063 VID 0 073 VID 0 083 1 2 3 55 VID 0 069 VID 0 079 VID 0 089 1 2 3 60 VID 0 075 VID 0 085 V...

Page 33: ...0 VID 0 188 VID 0 198 VID 0 208 1 2 3 Table 2 13 Quad Core Intel Xeon Processor X5482 VCC Static and Transient Tolerance Sheet 2 of 2 ICC A VCC_Max V VCC_Typ V VCC_Min V Notes Table 2 14 Quad Core Intel Xeon Processor X5400 Series Quad Core Intel Xeon Processor E5400 Series Quad Core Intel Xeon Processor L5400 Series VCC Static and Transient Tolerance Sheet 1 of 2 ICC A VCC_Max V VCC_Typ V VCC_Min...

Page 34: ...re not applicable for the Quad Core Intel Xeon Processor E5400 Series 5 ICC values greater than 60A are not applicable for the Quad Core Intel Xeon Processor L5400 Series 6 ICC values greater than 48A are not applicable for the Quad Core Intel Xeon Processor L5408 110 VID 0 138 VID 0 153 VID 0 168 1 2 3 4 5 6 115 VID 0 144 VID 0 159 VID 0 174 1 2 3 4 5 6 120 VID 0 150 VID 0 165 VID 0 180 1 2 3 4 5...

Page 35: ... Core Intel Xeon Processor X5482 VCC Static and Transient Tolerance Load Lines VID 0 000 VID 0 050 VID 0 100 VID 0 150 VID 0 200 VID 0 250 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 Icc A Vcc V VCC Maximum VCC Typical VCC Minimum ...

Page 36: ...Load Lines VID 0 000 VID 0 020 VID 0 040 VID 0 060 VID 0 080 VID 0 100 VID 0 120 VID 0 140 VID 0 160 VID 0 180 VID 0 200 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 Icc A Vcc V VCC Maximum VCC Typical VCC Minimum VID 0 000 VID 0 020 VID 0 040 VID 0 060 VID 0 080 VID 0 100 VID 0 120 VID 0 140 VID 0 160 VID 0 180 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 ...

Page 37: ...at will be interpreted as a logical low value 3 VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 VIH and VOH may experience excursions above VTT However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Refer to processor I O Buffer Models for I V characteristics Measu...

Page 38: ... VID VOS_MAX VOS_MAX is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Table 2 16 CMOS Signal Input Output Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage 0 10 0 00 0 3 VTT...

Page 39: ...rm design guidelines for specific implementation details In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 8 for details on which signals do not include on die termination Please refer to Table 2 19 for RTT values Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF_DATA_...

Page 40: ...age is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1 3 VHavg is the statistical average of the VH measured by the oscilloscope 4 Overshoot is defined as the absolute value of the maximum voltage 5 Undershoot is defined as the absolute value of the minimum voltage 6 Ringback Margin is defined as the absolute voltage difference between...

Page 41: ... of all crossing voltages as defined in note 3 12 Measured from 200 mV to 200 mV on the differential waveform derived from REFCLK minus REFCLK The signal must be monotonic through the measurement region for rise and fall time The 400 mV measurement window is centered on the differential zero crossing See Figure 2 15 Figure 2 12 Electrical Test Circuit Figure 2 13 Differential Clock Waveform Vtt 55...

Page 42: ...rential Clock Crosspoint Specification Figure 2 15 Differential Rising and Falling Edge Rates 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 VHavg mV Crossing Point mV 550 mV 250 mV 250 0 5 VHavg 700 550 0 5 VHavg 700 ...

Page 43: ...s shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TIM Processor Core die Package Substrate Landside capacitors Package Lands Note This drawing is not to scale and is for reference only 3 1 Package Mechanical Drawings The package mechanical drawings are shown in Figure 3 2 through Figure 3 4 The drawings include dimensions necessary to design a ther...

Page 44: ...ntial IHS flatness variation with socket load plate actuation and installation of the cooling solution are available in the processor Thermal Mechanical Design Guidelines Figure 3 2 Quad Core Intel Xeon Processor 5400 Series Package Drawing Sheet 1 of 3 ...

Page 45: ...45 Mechanical Specifications Figure 3 3 Quad Core Intel Xeon Processor 5400 Series Package Drawing Sheet 2 of 3 ...

Page 46: ...ations 46 Note The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial processors Figure 3 4 Quad Core Intel Xeon Processor 5400 Series Package Drawing Sheet 3 of 3 ...

Page 47: ...rization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 6 Test condition used a heatsink mass of 1 lbm with 50 g acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility...

Page 48: ...rtion Specifications The Quad Core Intel Xeon Processor 5400 Series can be inserted and removed 15 times from an LGA771 socket which meets the criteria outlined in the LGA771 Socket Design Guidelines 3 6 Processor Mass Specifications The typical mass of the Quad Core Intel Xeon Processor 5400 Series is 21 5 grams 0 76 oz This includes all components which make up the entire processor product 3 7 P...

Page 49: ... GROUP1LINE4 GROUP1LINE5 ATPO S N Legend GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Mark Text Production Mark 3200DP 12M 1600 Intel Xeon Proc SXXX COO i M 07 FPO Figure 3 6 Processor Land Coordinates Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G ...

Page 50: ... 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Socket 771 Quadrants Bottom View VCC VSS Data Address Common Clock Async ...

Page 51: ...ut A22 AD6 Source Sync Input Output A23 AA5 Source Sync Input Output A24 AB5 Source Sync Input Output A25 AC5 Source Sync Input Output A26 AB4 Source Sync Input Output A27 AF5 Source Sync Input Output A28 AF4 Source Sync Input Output A29 AG6 Source Sync Input Output A30 AG4 Source Sync Input Output A31 AG5 Source Sync Input Output A32 AH4 Source Sync Input Output A33 AH5 Source Sync Input Output A...

Page 52: ... 4 1 Land Listing by Land Name Sheet 3 of 20 Pin Name Pin No Signal Buffer Type Direction D33 E15 Source Sync Input Output D34 E16 Source Sync Input Output D35 G18 Source Sync Input Output D36 G17 Source Sync Input Output D37 F17 Source Sync Input Output D38 F18 Source Sync Input Output D39 E18 Source Sync Input Output D40 E19 Source Sync Input Output D41 F20 Source Sync Input Output D42 E21 Sourc...

Page 53: ...ut Output MCERR AB3 Common Clk Input Output MS_ID0 W1 Power Other Output MS_ID1 V1 Power Other Output PECI G5 Power Other Input Output PROCHOT AL2 Open Drain Output PWRGOOD N1 CMOS ASync Input REQ0 K4 Source Sync Input Output REQ1 J5 Source Sync Input Output REQ2 M6 Source Sync Input Output REQ3 K6 Source Sync Input Output REQ4 J6 Source Sync Input Output RESERVED AM6 RESERVED A20 Table 4 1 Land L...

Page 54: ...Other VCC AD24 Power Other Table 4 1 Land Listing by Land Name Sheet 7 of 20 Pin Name Pin No Signal Buffer Type Direction VCC AD25 Power Other VCC AD26 Power Other VCC AD27 Power Other VCC AD28 Power Other VCC AD29 Power Other VCC AD30 Power Other VCC AD8 Power Other VCC AE11 Power Other VCC AE12 Power Other VCC AE14 Power Other VCC AE15 Power Other VCC AE18 Power Other VCC AE19 Power Other VCC AE...

Page 55: ... Power Other Table 4 1 Land Listing by Land Name Sheet 9 of 20 Pin Name Pin No Signal Buffer Type Direction VCC AK26 Power Other VCC AK8 Power Other VCC AK9 Power Other VCC AL11 Power Other VCC AL12 Power Other VCC AL14 Power Other VCC AL15 Power Other VCC AL18 Power Other VCC AL19 Power Other VCC AL21 Power Other VCC AL22 Power Other VCC AL25 Power Other VCC AL26 Power Other VCC AL29 Power Other ...

Page 56: ...29 Power Other Table 4 1 Land Listing by Land Name Sheet 11 of 20 Pin Name Pin No Signal Buffer Type Direction VCC M30 Power Other VCC M8 Power Other VCC N23 Power Other VCC N24 Power Other VCC N25 Power Other VCC N26 Power Other VCC N27 Power Other VCC N28 Power Other VCC N29 Power Other VCC N30 Power Other VCC N8 Power Other VCC P8 Power Other VCC R8 Power Other VCC T23 Power Other VCC T24 Power...

Page 57: ...er Other VSS AB1 Power Other VSS AB23 Power Other Table 4 1 Land Listing by Land Name Sheet 13 of 20 Pin Name Pin No Signal Buffer Type Direction VSS AB24 Power Other VSS AB25 Power Other VSS AB26 Power Other VSS AB27 Power Other VSS AB28 Power Other VSS AB29 Power Other VSS AB30 Power Other VSS AB7 Power Other VSS AC3 Power Other VSS AC6 Power Other VSS AC7 Power Other VSS AD4 Power Other VSS AD7...

Page 58: ...0 Power Other Table 4 1 Land Listing by Land Name Sheet 15 of 20 Pin Name Pin No Signal Buffer Type Direction VSS AK23 Power Other VSS AK24 Power Other VSS AK27 Power Other VSS AK28 Power Other VSS AK29 Power Other VSS AK30 Power Other VSS AK5 Power Other VSS AK7 Power Other VSS AL10 Power Other VSS AL13 Power Other VSS AL16 Power Other VSS AL17 Power Other VSS AL20 Power Other VSS AL23 Power Othe...

Page 59: ...22 Power Other Table 4 1 Land Listing by Land Name Sheet 17 of 20 Pin Name Pin No Signal Buffer Type Direction VSS F4 Power Other VSS F7 Power Other VSS H10 Power Other VSS H11 Power Other VSS H12 Power Other VSS H13 Power Other VSS H14 Power Other VSS H17 Power Other VSS H18 Power Other VSS H19 Power Other VSS H20 Power Other VSS H21 Power Other VSS H22 Power Other VSS H23 Power Other VSS H24 Pow...

Page 60: ...V3 Power Other VSS V30 Power Other Table 4 1 Land Listing by Land Name Sheet 19 of 20 Pin Name Pin No Signal Buffer Type Direction VSS V6 Power Other VSS V7 Power Other VSS W4 Power Other VSS W7 Power Other VSS Y2 Power Other VSS Y5 Power Other VSS Y7 Power Other VSS_DIE_SENSE AN4 Power Other Output VSS_DIE_SENSE2 AL7 Power Other Output VTT A25 Power Other VTT A26 Power Other VTT B25 Power Other V...

Page 61: ...er AA28 VSS Power Other AA29 VSS Power Other AA3 VSS Power Other AA30 VSS Power Other AA4 A21 Source Sync Input Output AA5 A23 Source Sync Input Output AA6 VSS Power Other AA7 VSS Power Other AA8 VCC Power Other AB1 VSS Power Other AB2 IERR Open Drain Output AB23 VSS Power Other AB24 VSS Power Other AB25 VSS Power Other AB26 VSS Power Other AB27 VSS Power Other AB28 VSS Power Other AB29 VSS Power ...

Page 62: ...Power Other Output Table 4 2 Land Listing by Land Number Sheet 3 of 20 Pin No Pin Name Signal Buffer Type Direction AE9 VCC Power Other AF1 TDO TAP Output AF10 VSS Power Other AF11 VCC Power Other AF12 VCC Power Other AF13 VSS Power Other AF14 VCC Power Other AF15 VCC Power Other AF16 VSS Power Other AF17 VSS Power Other AF18 VCC Power Other AF19 VCC Power Other AF2 BPM4 Common Clk Output AF20 VSS...

Page 63: ...6 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 5 of 20 Pin No Pin Name Signal Buffer Type Direction AH27 VCC Power Other AH28 VCC Power Other AH29 VCC Power Other AH3 VSS Power Other AH30 VCC Power Other AH4 A32 Source Sync Input Output AH5 A33 Source Sync Input Output AH6 VSS Power Other AH7 RESERVED AH8 VCC Power Other AH9 VCC Power Other AJ1 BPM1 Common Clk Output AJ10 VSS Power ...

Page 64: ...e 4 2 Land Listing by Land Number Sheet 7 of 20 Pin No Pin Name Signal Buffer Type Direction AL18 VCC Power Other AL19 VCC Power Other AL2 PROCHOT Open Drain Output AL20 VSS Power Other AL21 VCC Power Other AL22 VCC Power Other AL23 VSS Power Other AL24 VSS Power Other AL25 VCC Power Other AL26 VCC Power Other AL27 VSS Power Other AL28 VSS Power Other AL29 VCC Power Other AL3 VSS Power Other AL30 ...

Page 65: ...ection B10 D10 Source Sync Input Output B11 VSS Power Other B12 D13 Source Sync Input Output B13 RESERVED B14 VSS Power Other B15 D53 Source Sync Input Output B16 D55 Source Sync Input Output B17 VSS Power Other B18 D57 Source Sync Input Output B19 D60 Source Sync Input Output B2 DBSY Common Clk Input Output B20 VSS Power Other B21 D59 Source Sync Input Output B22 D63 Source Sync Input Output B23 ...

Page 66: ...Power Other D28 VTT Power Other Table 4 2 Land Listing by Land Number Sheet 11 of 20 Pin No Pin Name Signal Buffer Type Direction D29 VTT Power Other D3 VSS Power Other D30 VTT Power Other D4 HIT Common Clk Input Output D5 VSS Power Other D6 VSS Power Other D7 D20 Source Sync Input Output D8 D12 Source Sync Input Output D9 VSS Power Other E1 RESERVED Power Other E10 D21 Source Sync Input Output E1...

Page 67: ...6 Source Sync Input Output G18 D35 Source Sync Input Output Table 4 2 Land Listing by Land Number Sheet 13 of 20 Pin No Pin Name Signal Buffer Type Direction G19 DSTBP2 Source Sync Input Output G2 COMP2 Power Other Input G20 DSTBN2 Source Sync Input Output G21 D44 Source Sync Input Output G22 D47 Source Sync Input Output G23 RESET Common Clk Input G24 RESERVED G25 RESERVED G26 RESERVED G27 RESERVE...

Page 68: ...ble 4 2 Land Listing by Land Number Sheet 15 of 20 Pin No Pin Name Signal Buffer Type Direction J9 VCC Power Other K1 LINT0 CMOS Async Input K2 VSS Power Other K23 VCC Power Other K24 VCC Power Other K25 VCC Power Other K26 VCC Power Other K27 VCC Power Other K28 VCC Power Other K29 VCC Power Other K3 A20M CMOS Async Input K30 VCC Power Other K4 REQ0 Source Sync Input Output K5 VSS Power Other K6 ...

Page 69: ...t P7 VSS Power Other Table 4 2 Land Listing by Land Number Sheet 17 of 20 Pin No Pin Name Signal Buffer Type Direction P8 VCC Power Other R1 COMP3 Power Other Input R2 VSS Power Other R23 VSS Power Other R24 VSS Power Other R25 VSS Power Other R26 VSS Power Other R27 VSS Power Other R28 VSS Power Other R29 VSS Power Other R3 FERR PBE Open Drain Output R30 VSS Power Other R4 A08 Source Sync Input O...

Page 70: ...TIN1 Power Other Input W23 VCC Power Other W24 VCC Power Other W25 VCC Power Other W26 VCC Power Other W27 VCC Power Other W28 VCC Power Other W29 VCC Power Other W3 RESERVED W30 VCC Power Other W4 VSS Power Other W5 A16 Source Sync Input Output W6 A18 Source Sync Input Output W7 VSS Power Other Table 4 2 Land Listing by Land Number Sheet 19 of 20 Pin No Pin Name Signal Buffer Type Direction W8 VC...

Page 71: ... O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction 2 ADS I O ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 37 3 lands All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the...

Page 72: ...ed on specific clock edges and sampled on specific clock edges 3 BPM5 BPM4 BPM3 BPM 2 1 BPM0 I O O I O O I O BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all FSB agents BPM4 provi...

Page 73: ...more the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high 3 DBI 3 0 I O DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data...

Page 74: ...ntel387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionalit...

Page 75: ...rted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents 2 LIN...

Page 76: ...r supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 2 18 and be followed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied t...

Page 77: ...e clock input for the processor Test Bus also known as the Test Access Port TDI I TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO O TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTHI 12 10 I TESTHI 12 10 must be connected ...

Page 78: ...ee the applicable platform design guide for implementation details VID 6 1 O VID 6 1 Voltage ID pins are used to support automatic selection of power supply voltages VCC These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are ...

Page 79: ...applicable thermal profile see Table 6 1 and Figure 6 1 for the Quad Core Intel Xeon Processor X5482 Table 6 3 and Figure 6 2 for the Quad Core Intel Xeon Processor X5400 Series Table 6 6 and Figure 6 3 for the Quad Core Intel Xeon Processor E5400 Series Table 6 8 and Figure 6 4 for the Quad Core Intel Xeon Processor L5400 Series and Table 6 11 and Figure 6 5 for the Quad Core Intel Xeon Processor...

Page 80: ...duced cooling capability represented by this thermal solution the probability of TCC activation and performance loss is increased Additionally utilization of a thermal solution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanent damage to the processor Intel has developed these thermal profiles to allow customers to choose the thermal solution a...

Page 81: ...el Xeon Processor X5482 is intended for dual processor workstations only Notes 1 Please refer to Table 6 2 for discrete points that constitute the thermal profile 2 Implementation of the Quad Core Intel Xeon Processor X5482 Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increase...

Page 82: ...rmal Profile Table Power W TCASE_MAX C 0 35 0 5 35 9 10 36 9 15 37 8 20 38 7 25 39 7 30 40 6 35 41 5 40 42 5 45 43 0 50 44 4 55 45 3 60 46 2 65 47 2 70 48 1 75 49 0 80 50 0 85 50 9 90 51 8 95 52 8 100 53 7 105 54 6 110 55 6 115 56 5 120 57 4 125 58 4 130 59 3 135 60 2 140 61 2 145 62 1 150 63 0 ...

Page 83: ...l Profile B is representative of a volumetrically constrained platform Please refer to Table 6 5 for discrete points that constitute the thermal profile 4 Implementation of the Quad Core Intel Xeon Processor X5400 Series Thermal Profile B will result in increased probability of TCC activation and measurable performance loss Furthermore utilization of thermal solutions that do not meet Thermal Prof...

Page 84: ...ssor X5400 Series Thermal Profile A Table Power W TCASE_MAX C 0 42 8 5 43 6 10 44 5 15 45 3 20 46 2 25 47 0 30 47 8 35 48 7 40 49 5 45 50 0 50 51 2 55 52 0 60 52 9 65 53 7 70 54 6 75 55 4 80 56 2 85 57 1 90 57 9 95 58 8 100 59 6 105 60 4 110 61 3 115 62 1 120 63 0 ...

Page 85: ...ations are defined at all VIDs found in Table 2 12 The Quad Core Intel Xeon Processor E5400 Series may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Table 6 5 Quad Core Intel Xeon Processor X5400 Series Thermal Profile B Table Power W TCASE_MAX C 0 43 5 5 44 6 10 45 7 15 46...

Page 86: ...Refer to the Quad Core Intel Xeon Processor 5400 Series Thermal Mechanical Design Guidelines TMDG for system and environmental implementation details Figure 6 3 Quad Core Intel Xeon Processor E5400 Series Thermal Profile 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 0 10 20 30 40 50 60 70 80 Pow er W Tcase C Thermal Profile Y 0 298 x 43 2 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 0 10 20 3...

Page 87: ...ase refer to Table 6 9 for discrete points that constitute the thermal profile 2 Implementation of the Quad Core Intel Xeon Processor L5400 Series Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See...

Page 88: ...cifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VIDs found in Table 2 12 The Quad Core Intel Xeon Processor L5408 may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements T...

Page 89: ...h NEBS Level 3 5 Utilization of a thermal solution that exceeds the Short Term Thermal Profile or which operates at the Short Term Thermal Profile for a duration longer than the limits specified in Note 4 above do not meet the processor s thermal specifications and may result in permanent damage to the processor 6 Refer to the Quad Core Intel Xeon Processor L5408 Series in Embedded Applications Th...

Page 90: ... Features 6 2 1 Intel Thermal Monitor Features Quad Core Intel Xeon Processor 5400 Series provides two thermal monitor features Intel Thermal Monitor 1 and Intel Thermal Monitor 2 The Intel Thermal Monitor 1 and Intel Thermal Monitor 2 must both be enabled in BIOS for the processor to be operating within specifications When both are enabled Intel Thermal Monitor 2 will be activated first and Intel...

Page 91: ...g a thermal solution The duty cycle for the TCC when activated by the Intel Thermal Monitor 1 is factory configured and cannot be modified The Intel Thermal Monitor 1 does not require any additional hardware software drivers or interrupt handling routines 6 2 1 2 Intel Thermal Monitor 2 The Quad Core Intel Xeon Processor 5400 Series adds supports for an Enhanced Thermal Monitor capability known as...

Page 92: ...wer consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operatin...

Page 93: ...ng TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum TCASE when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature or the case temperature Therm...

Page 94: ...of the PECI topology in a system with Quad Core Intel Xeon Processor 5400 Series PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2Kbps to 2Mbps The PECI interface on the Quad Core Intel Xeon Processor 5400 Series is disabled by default and must be enabled ...

Page 95: ...r DTS also implements an averaging algorithm that filters the incoming data This is an alpha beta filter with coefficients of 0 5 and is expressed mathematically as Current_filtered_temp Previous_filtered_temp 2 new_sensor_temp 2 This filtering algorithm is fixed and cannot be changed It is on by default and can be turned off in BIOS Host controllers should utilize the min max sample times to dete...

Page 96: ...tain scenarios where PECI is known to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not guaranteed to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due ...

Page 97: ...to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled via the BIOS for the processor to ...

Page 98: ...can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts 7 2 2 2 Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT s...

Page 99: ...nning in HALT state The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus to core frequency ratio back to the original value Table 7 2 Extended HALT Maximum Power Symbol Parameter Min Typ Max Unit Notes 1 PEXTENDED_HALT Quad Core Intel Xeon Processor X5482...

Page 100: ...en to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A trans...

Page 101: ... stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT state as appropriate 7 2 4 2 Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state ...

Page 102: ...either of the processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at red...

Page 103: ...d lower TDPs will include an aluminum extruded 1U passive 3U active combination solution or an aluminum extruded 2U passive heatsink The 1U passive 3U active combination solution in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue The 1U passive 3U active combination s...

Page 104: ...ecifications 104 Figure 8 1 Boxed Quad Core Intel Xeon Processor 5400 Series 1U Passive 3U Active Combination Heat Sink With Removable Fan Figure 8 2 Boxed Quad Core Intel Xeon Processor 5400 Series 2U Passive Heat Sink ...

Page 105: ...e mechanical specifications of the boxed processor 8 2 1 Boxed Processor Heat Sink Dimensions CEK The boxed processor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8 4 through Figure...

Page 106: ...Boxed Processor Specifications 106 Figure 8 4 Top Side Board Keepout Zones Part 1 ...

Page 107: ...107 Boxed Processor Specifications Figure 8 5 Top Side Board Keepout Zones Part 2 ...

Page 108: ...Boxed Processor Specifications 108 Figure 8 6 Bottom Side Board Keepout Zones ...

Page 109: ...109 Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones ...

Page 110: ...Boxed Processor Specifications 110 Figure 8 8 Volumetric Height Keep Ins ...

Page 111: ...111 Boxed Processor Specifications Figure 8 9 4 Pin Fan Cable Connector For Active CEK Heat Sink ...

Page 112: ...Boxed Processor Specifications 112 Figure 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink ...

Page 113: ... loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures All components of the CEK heat sink solution will be captive to the heat sink and will only require a Phillips screwdriver to attach to the chassis pan When installing the CEK the CEK screws should be tightened until they...

Page 114: ... 1U Passive 3U Active Combination Heat Sink Solution 1U Rack Passive In the 1U configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0 38 in H2O 25 5 m3 hr at 94 6 Pa of flow impedance The duct should be carefully designed to minimize the airflow bypass Table 8 1 PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution Descripti...

Page 115: ...ed by other system components Meeting the processor s temperature specification is the responsibility of the system integrator 8 3 2 3 2U Passive Heat Sink Solution 2U Rack or Pedestal In the 2U passive configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 27 cfm at 0 182 in H2O 45 9 m3 hr at 45 3 Pa of flow impedance The duct should be carefully desig...

Page 116: ...Boxed Processor Specifications 116 ...

Page 117: ...eneral the information in this chapter may be used as a basis for including all run control tools in Quad Core Intel Xeon Processor 5400 Series based system designs including tools from vendors other than Intel Note The debug port and JTAG signal chain must be designed into the processor board to utilize the XDP for debug purposes except for interposer solutions 9 2 Target System Implementation 9 ...

Page 118: ...ake sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include differerent requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI 9 3 2 Electrical Considerations The LAI will also affect the electrical per...

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