IEI Technology IMBA-X9654, User Manual, Page: 37 / 266

IMBA-X9654 ATX Motherboard
Page 19
chip-to-chip connection interface to Intel ICH8
2GB/s (1GB/s in each direction) bus speed
32-bit downstream address
100 MHz reference clock (shared with PCI Express Graphics Attach)
APIC and MSI interrupt messaging support
Message Signaled Interrupt (MSI) messages
SMI, SCI and SERR error indication
DMA, floppy drive, and LPC bus master
2.5 Intel
®
ICH8DO Southbridge Chipset
2.5.1 Intel
®
ICH8DO Overview
The Intel® ICH8DO southbridge chipset is connected to the Intel® Q965 northbridge
GMCH through the chip-to-chip Direct Media Interface (DMI). Some of the features of the
Intel® ICH8DO are listed below.
Complies with PCI Express Base Specification, Revision 1.1
Complies with PCI Local Bus Specification, Revision 2.3 and supports 33MHz
PCI operations
Supports ACPI Power Management Logic
Contains:
o
Enhanced DMA controller
o
Interrupt controller
o
Timer functions
Integrated SATA host controller with DMA operations and AHCI support
interfaced to six SATA connectors on the IMBA-X9654
Supports the eight USB 2.0 devices on the IMBA-X9654 with five UHCI
controllers and two EHCI controllers
Integrated 10/100/1000 GbE MAC with System Defense
Complies with System Management Bus (SMBus) Specification, Version 2.0
Supports Intel High Definition Audio
Supports Intel® Matrix Storage Technology
Supports Intel® Active Management Technology (ICH8DO only)
Low Pin Count (LPC) interface
Firmware Hub (FWH) interface support