IDT 89HPES12N3, User Manual, Page: 92 / 158

IDT Transparent Mode Operation Downstream Port B Configuration Space Registers
PES12N3 User Manual 9 - 12 June 7, 2006
Notes
0x028 DWord PB_PMBASEU PMBASEU - Prefetchable Memory Base Upper (0x028) on page
9-24
0x02C DWord PB_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on page
9-24
0x030 Word PB_IOBASEU IOBASEU - I/O Base Upper (0x030) on page 9-24
0x032 Word PB_IOLIMITU IOLIMITU - I/O Limit Upper (0x032) on page 9-25
0x034 Byte PB_CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 9-25
0x038 DWord PB_EROMBASE EROMBASE - Expansion ROM Base Address (0x038) on page
9-25
0x03C Byte PB_INTRLINE INTRLINE - Interrupt Line (0x03C) on page 9-25
0x03D Byte PB_INTRPIN INTRPIN - Interrupt PIN (0x03D) on page 9-25
0x03E Word PB_BCTRL BCTRL - Bridge Control (0x03E) on page 9-26
0x040 DWord PB_PCIECAP PB_PCIECAP - PCI Express Capability (0x040) on page 9-13
0x044 DWord PB_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page
9-27
0x048 Word PB_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-28
0x04A Word PB_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-29
0x04C DWord PB_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 9-
30
0x050 Word PB_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-30
0x052 Word PB_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-31
0x054 DWord PB_PCIESCAP PCIESCAP - PCI Express Slot Capabilities (0x054) on page 9-
32
0x058 Word PB_PCIESCTL PCIESCTL - PCI Express Slot Control (0x058) on page 9-33
0x05A Word PB_PCIESSTS PCIESSTS - PCI Express Slot Status (0x05A) on page 9-35
0x070 DWord PB_PMCAP PMCAP - PCI Power Management Capabilities (0x070) on page
9-36
0x074 DWord PB_PMCSR PMCSR - PCI Power Management Control and Status (0x074)
on page 9-36
0x078 DWord PB_PMPC PMPC - PCI Power Management Proprietary Control (0x078) on
page 9-37
0x07C DWord PB_MSICAP MSICAP - Message Signaled Interrupt Capability and Control
(0x07C) on page 9-39
0x080 DWord PB_MSIADDR MSIADDR - Message Signaled Interrupt Address (0x080) on
page 9-39
0x084 DWord PB_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address
(0x084) on page 9-40
0x088 DWord PB_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data
(0x088) on page 9-40
0x0F4 Word PB_INTSTS INTSTS - Interrupt Status (0x0F4) on page 9-49
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
Table 9.7 Downstream Port B Configuration Space Registers (Part 2 of 3)