IDT 89HPES12N3, User Manual

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IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition
PES12N3 User Manual 9 - 30 June 7, 2006
Notes
PCIELCAP - PCI Express Link Capabilities (0x04C)
PCIELCTL - PCI Express Link Control (0x050)
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 MAXLNKSPD RO 0x1 Maximum Link Speed. This field is hardwired to 0x1 to
indicate 2.5 Gbps.
9:4 MAXLNKWDTH RWL 0x8 Maximum Link Width. This field indicates the maximum
link width of the given PCI Express link. This field may be
overridden to allow the link width to be forced to a smaller
value. Setting this field to a invalid or reserved value results
in x1 being used.
1 -
(x1) x1 link width
2 - (x2) x2 link width
4 - (x4) x4 link width
8 - (x8) x8 link width
others- reserved
11:10 ASPMS RO 0x3 Active State Power Management (ASPM) Support. This
field is hardwired to 0x3 to indicate L0s and L1 Support.
14:12 L0SEL RWL see text L0s Exit Latency. This field indicates the L0s exit latency
for the given PCI Express link. This field depends on
whether a common or separate reference clock is used.
When separate clocks are used, 1 µ s to 2 µ s is reported
with a read-only value of 0x5.
When a common clock is used, 256 ns to 512 ns is
reported with a read-only value of 0x3
17:15 L1EL RWL 0x2 L1 Exit Latency. This field indicates the L1 exit latency for
the given PCI Express link. Transitioning from L1 to L0
always requires 2.3 µ s. Therefore, a value 2 µ s to less
than 4 µ s is reported with a default value of 0x2.
23:18 Reserved RO 0x0 Reserved field.
31:24 PORTNUM RO port A - 0x0
Port B - 0x1
Port C - 0x2
Port Number. This field indicates the PCI express port
number.
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 ASPM RW 0x0 Active State Power Management (ASPM) Control. This
field controls the level of ASPM supported by the link. The
initial value corresponds to disabled. The value contained
in Serial EEPROM may override this default value
0x0 - (disabled) disabled
0x1 - (l0s) L0s enable entry
0x2 - (l1) L1 enable entry
0x3 - (l0sl1) L0s and L1 enable entry
2 Reserved RO 0x0 Reserved field.
3 RCB RO 0x0 Read Completion Boundary. This field is not applicable
and is hardwired to zero.