IDT 89HPES12N3, User Manual

Page: 31 / 158

IDT Clocking, Reset, and Initialization Reset
PES12N3 User Manual 2 - 3 June 7, 2006
Notes
Reset
PCI Express® defines two reset categories: fundamental reset and hot reset. A fundamental reset
causes all associated logic to be returned to an initial state. A hot reset causes all associated logic to be
returned to an initial state, but does not cause the state of register fields denoted as “sticky” to be modified.
There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset is a fundamental reset that
occurs without removal of power.
A summary of reset conditions and their effect is exhibited in Table 2.3.
RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express
fundamental reset, the PES12N3 executes the reset procedure
and remains in a reset state with the Master and Slave
SMBuses active. This allows software to read and write regis-
ters internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit
is cleared in the PA_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in
the PA_SWCTL register.
TSTRSVD N Reserved. Reserved for future test mode. Must be tied to
ground.
SWMODE[3:0] N Switch Mode. These configuration pins determine the
PES12N3 switch operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - 10-bit loopback test mode
0x9 - Reserved
0xA - Internal pseudo random bit stream self-test test mode
0xB - External pseudo random bit stream self-test test mode
0xC - Reserved
0xD - SerDes broadcast test mode
0xE - Reserved
0xF - Reserved
Fund.
Reset
Global
Hot
Reset to
Entire
Device
Global
Hot
Reset to
Downstr
eam
Ports
Local
Hot
Reset
Master SMBus Y N N N
Slave SMBus Y N N N
Serial EEPROM Initial-
ization Y
if mode
requires it
N N N
Table 2.3 Reset Conditions and Their Effect (Part 1 of 2)
Signal
May Be
Overridden
Description
Table 2.2 Boot Configuration Vector Signals (Part 2 of 2)