IDT 89HPES12N3, User Manual

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IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition
PES12N3 User Manual 9 - 49 June 7, 2006
Notes
Extended Configuration Space Access and INTx Status Registers
INTSTS - Interrupt Status (0x0F4)
ECFGADDR - Extended Configuration Space Access Address (0x0F8)
25 IOEXTM RW 0x0 I/O Expander Test Mode. Setting this bit puts the I/O
expander into a test mode. In this test mode, Port B and
Port C hot-plug output signals generated by the core are
ignored and values supplied to the I/O expander corre-
spond to value written to the PBHPS and PCHPS fields.
30:26 Reserved RO 0x0 Reserved field.
31 DONE RW1C 0x0 I/O Expander Operation Done. This bit is set when the
RELOADI-OEX bit in this register or the IOEADDR field in
the SMBUSSTS register is written and the corresponding
I/O expander SMBus transaction completes; or when the
I/O expander is in test mode (i.e., IOEXTM bit set), the
PBHPS or PCHPS fields are written, and the correspond-
ing I/O expander SMBus transaction updating the I/O
expander outputs completes.
Bit
Field
Field
Name
Type
Default
Value
Description
0 INTA RO 0x0 INTA Aggregated State. Aggregated port state for INTA.
0x0 - (negated) INTA negated
0x1 - (asserted) INTA asserted
1 INTB RO 0x0 INTB Aggregated State. Aggregated port state for INTB.
0x0 - (negated) INTB negated
0x1 - (asserted) INTB asserted
2 INTC RO 0x0 INTC Aggregated State. Aggregated port state for INTC.
0x0 - (negated) INTC negated
0x1 - (asserted) INTC asserted
3 INTD RO 0x0 INTD Aggregated State. Aggregated port state for INTD.
0x0 - (negated) INTD negated
0x1 - (asserted) INTD asserted
31:4 Reserved RO 0x0 Reserved.
Bit
Field
Field
Name
Type
Default
Value
Description
0:1 Reserved RO 0x0 Reserved.
7:2 REG RW 0x0 Register Number. This field selects the configuration reg-
ister number as defined by Section 7.2.2 of the PCI
Express Base Specification, Rev. 1.0a
11:8 EREG RW 0x0 Extended Register Number. This field selects the
extended configuration register number as defined by Sec-
tion 7.2.2 of the PCI Express Base Specification, Rev. 1.0a
Bit
Field
Field
Name
Type
Default
Value
Description