IDT 89HPES12N3, User Manual

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IDT Test and Debug SerDes Test Clock
PES12N3 User Manual 10 - 5 June 7, 2006
Notes
SerDes Test Clock
Each of the six on-chip PLLs generates a 250 MHz clock. The output of any of these PLL clocks divided
by four (i.e., a 62.5 MHz clock) may be output on GPIO alternate function pins. In addition, the 2.5 GHz
recovered SerDes receive clock from any of the 24 lanes divided by 40 (i.e., 62.5 MHz) may be selected.
SerDes Test Clock 0 (TSTCLK0) is an alternate function of GPIO[6]. The clock output on this alternate
function is selected by the Test Clock 0 Select (TSTCLK0SEL) field in the SWCTL register. SerDes Test
Clock 1 (TSTCLK1) is an alternate function of GPIO[7]. The clock output on this alternate function is
selected by the Test Clock 1 Select (TSTCLK1SEL) field in the SWCTL register.