IDT 89HPES12N3, User Manual

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IDT SMBus Interfaces SMBus Registers
PES12N3 User Manual 7 - 2 June 7, 2006
Notes
some systems, this external SMBus master interface may be implemented using general purpose I/O pins
on a processor or microcontroller, and thus may not support SMBus arbitration. To support these systems,
the PES12N3 may be configured to operate in a split configuration as shown in Figure 7.1(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus
multi-master arbitration is not required.
SMBus Registers
Bit
Field
Field
Name
Type
Default
Value
Description
0 Reserved RO 0x0 Reserved field.
7:1 SSMBADDR RO HWINIT Slave SMBus Address. This field contains the SMBus
address assigned to the slave SMBus interface.
8 Reserved RO 0x0 Reserved field.
15:9 MSMBADDR RO HWINIT Master SMBus Address. This field contains the SMBus
address assigned to the master SMBus interface.
16 Reserved RO 0x0 Reserved field.
23:17 IOEADDR RWL 0x0 Hot-plug I/O Expander Master SMBus Address. This
field contains SMBus address assigned to the hot-plug I/O
expander on the master SMBus interface.
24 EEPROM-
DONE
RO 0x0 Serial EEPROM Initialization Done. When the switch is
configured to operate in a mode in which serial EEPROM
initialization occurs during a fundamental reset, this bit is
set when serial EEPROM initialization completes or when
an error is detected.
25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected
NACK is observed during a master SMBus transaction.
The setting of this bit may indicate the following: that the
addressed device does not exist on the SMBus (i.e.,
addressing error); data is unavailable or the device is
busy; an invalid command was detected by the slave; or
invalid data was detected by the slave.
26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus inter-
face loses arbitration for the SMBus, it automatically re-
arbitrates for the SMBus. If the master SMBus interface
loses 16 consecutive arbitration attempts, then the trans-
action is aborted and this bit is set.
27 OTHERERR RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP
condition is detected by the master SMBus interface.
28 ICSERR RW1C 0x0 Initialization Checksum Error. This bit is set if an invalid
checksum is computed during Serial EEPROM initializa-
tion or when a configuration done command is not found in
the serial EEPROM.
29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is set
if an attempt is made to initialize via serial EEPROM a reg-
ister that is not defined in the corresponding PCI configu-
ration space.
31:30 Reserved RO 0x0 Reserved field.
Table 7.1 SMBUSSTS - SMBus Status