IDT 89HPES12N3, User Manual, Page: 119 / 158

IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition
PES12N3 User Manual 9 - 39 June 7, 2006
Notes
Message Signaled Interrupt Capability Structure
MSICAP - Message Signaled Interrupt Capability and Control (0x07C)
MSIADDR - Message Signaled Interrupt Address (0x080)
31 MCS RW 0x0 Mode Configuration Switch. When this bit is set to zero,
the PMPC register is configured as Mode1, shown in the
Mode1 table. When this bit is set to one, the register is con-
figured as Mode2, shown in this table.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 CAPID RO 0x5 Capability ID. The value of 0x5 identifies this capability as
a MSI capability structure.
15:8 NXTPTR RO 0x0 Next Pointer. This field contains a pointer to the next
capability structure. This field is set to 0x0 indicating that it
is the last capability.
16 EN RW 0x0 Enable. This bit enables MSI.
0x0 - (disable) disabled
0x1 - (enable) enabled
19:17 MMC RO 0x0 Multiple Message Capable. This field contains the num-
ber of requested messages. The transparent bridge
requests one message.
22:20 MME RO 0x0 Multiple Message Enable. Hardwired to one message.
23 A64 RO 0x1 64-bit Address Capable. The transparent bridge is capa-
ble of generating messages using a 64-bit address.
31:24 Reserved RO 0x0 Reserved.
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 Reserved RO 0x0 Reserved.
31:2 ADDR RW 0x0 Message Address. This field specifies the lower portion of
the DWORD address of the MSI memory write transaction.
Bit
Field
Field
Name
Type
Default
Value
Description