53
ICS1890
MII - Transmit Clock Tolerance
Note: TXCLK Duty Cycle = REF_IN Duty Cycle ±5%.
MII - Receive Clock Behavior
T#
PARAMETER (condition)
MIN
TYP
MAX
UNITS
t1
TXCLK Duty Cycle
35
50
65
%
t2a
TXCLK Period (100Base-T/MII Interface)
-
40
-
ns
t2b
TXCLK Period (10Base-T/MII Interface)
-
400
-
ns
t2c
TXCLK Period (100Base-T/100M Stream Interface)
-
40
-
ns
t2d
TXCLK Period (10Base-T/10M Serial Interface)
-
100
-
ns
T#
PARAMETER (condition)
MIN
TYP
MAX
UNITS
t1
RXCLK Duty Cycle
45
50
55
%
t2a
RXCLK Period (100Base-T/MII Interface)
-
40
-
ns
t2b
RXCLK Period (10Base-T/MII Interface)
-
400
ns
t2c
RXCLK Period (100Base-T/100M Stream Interface)
-
40
ns
t2d
RXCLK Period (10Base-T/10M Serial Interface)
-
100
ns
t4
RXDV Asserted Nominal Clock to Recovered Clock
Cycle Extension
-
-
65
ns
Summary of Contents for PHYceiver ICS1890
Page 49: ...49 ICS1890 Pin Configuration...