ICS PHYceiver ICS1890, General Description Manual

Page: 38 / 66

38
ICS1890
Receive Data Valid RXDV
Receive Data Valid (RXDV) is generated by the ICS1890 . It
indicates that the ICS1890 is recovering and decoding data
nibbles on the Receive Data (RXD) data lines synchronous
with the Receive Data Clock (RXCLK). It is the responsibility
of the MAC to frame the nibbles since the ICS1890 has no
knowledge of the frame structure and is merely a “nibble”
processor. The ICS1890 asserts RXDV when it detects and
recovers the pre-amble or the start of stream delimiter (SSD)
and de-asserts it following the last data nibble or upon detection
of a signal error. RXDV is synchronous with the Receive Data
Clock (RXCLK).
Receive Data 3 RXD3
Receive Data 3 (RXD3) is the most significant bit of the receive
data nibble. RXD is sourced by the ICS1890 . When Receive
Data Valid (RXDV) is asserted by the ICS1890 , it will
transfer the 4th bit of the symbol synchronously with Receive
Clock (RXCLK).
Receive Data 2 RXD2
Receive Data 2 (RXD2) is sourced by the ICS1890 . When
Receive Data Valid (RXDV) is asserted by the ICS1890 , it
will transfer the 3rd bit of the symbol synchronously with
Receive Clock (RXCLK).
Receive Data 1 RXD1
Receive Data 1 (RXD1) is sourced by the ICS1890 . When
Receive Data Valid (RXDV) is asserted by the ICS1890 , it
will transfer the 2nd bit of the symbol synchronously with
Receive Clock (RXCLK).
Receive Data 0 RXD0
Receive Data 0 (RXD0) is the least significant bit of the receive
data nibble. RXD0 is sourced by the ICS1890 . When Receive
Data Valid (RXDV) is asserted by the ICS1890 , it will
transfer the 1st bit of the symbol synchronously with Receive
Clock (RXCLK).
Receive Error RXER
In 100 Mbps mode, the ICS1890 detects two types of receive
errors, errors occurring during the reception of valid frames
and an error condition known as false carrier detect. False
carrier detect is signaled so that repeater applications can
prevent the propagation of false carrier detection. RXER always
transitions synchronously with RXCLK.
The assertion of Receive Error (RXER) for one or more
clock periods during the period when RXDV is asserted
(receiving a frame) indicates that the ICS1890 has detected
a read channel error. There are three sources of read channel
error: loss of receive signal, failure of the PLL to lock and
invalid symbol detection. RXER may also be asserted when
RXDV is de-asserted. The ICS1890 will assert RXER and set
RXD(3:0) to 1110 if a false carrier is detected. For a good
carrier to be detected, the ICS1890 looks continuously at the
incoming IDLE stream (1111...) for two non-contiguous
logic zeroes and then checks for the SSD of “JK.” In the event
that two non-contiguous logic zeroes are detected but the JK
symbol pair is not, then a false carrier condition is signaled
and the IDLE condition is re-entered.
Carrier Sense CRS
The ICS1890 asserts Carrier Sense (CRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are idle in half duplex mode. CRS is not synchronous
to either the transmit or receive clocks.
In full duplex mode and repeater mode, CRS is asserted only
on receive activity.
Collision Detected COL
The ICS1890 asserts Collision Detected (COL) when it
detects a receive carrier (non-idle condition) while transmitting
(TXEN asserted).
In the 10 Mbps mode, the non-idle condition is detected by
monitoring the unsquelched receive signal. In the 100 Mbps
mode, the non-idle condition is detected by two non-contiguous
zeros in any 10-bit code group. COL is not synchronous to
either the transmit or receive clocks.
In full duplex mode, COL is disabled and always remains low.
In the 10 Mbps Node mode, COL will also be asserted as part
of the signal quality error test (SQE). This behavior can be
suppressed with the SQE Test Inhibit bit (18:2).