46
ICS1890
Phy Address 4 - Receive Data LED
P4RD
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 16 is set in the
configuration register.
The
ICS1890
sets this bit to the appropriate value to turn on
the LED when receive data is detected. This signal is stretched
ensure that a single packet will be seen. If the packet stream
is continuous, the LED will appear permanently on.
Phy Address 3 - Transmit Data LED
P3TD
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 8 is set in the
configuration register.
The
ICS1890
sets this bit to the appropriate value to turn on
the LED when transmit data is detected. This signal is stretched
to ensure that a single packet will be seen. If the packet stream
is continuous, the LED will appear permanently on.
Phy Address 2 - Link Integrity LED
P2LI
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 4 is set in the
configuration register.
The
ICS1890
sets this bit to the appropriate value to turn on
the LED when the Link Integrity status is OK.
Phy Address 1 - Collision LED
P1CL
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 2 is set in the
configuration register.
The
ICS1890
sets this bit to the appropriate value to turn on
the LED when a collision is detected. This signal is stretched
to ensure that a single collision will be seen. If the collisions
are continuous, the LED will appear permanently on.
Phy Address 0 - Activity LED
P0AC
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 1 is set in the
configuration register.
The
ICS1890
sets this bit to the appropriate value to turn on
the LED when either transmit or receive activity is detected.
This signal is stretched to ensure that a single activity event
will be seen. If the activity is continuous, the LED will appear
permanently on.
Power Supply
These 7 VDD and 8 VSS pins supply power to the
ICS1890
device.
ICS1890 Power Supply Isolation and Filtering
It is important to properly isolate the
ICS1890
10/100Base-
TX Physical Layer Device from noise sources in a system
design. There are two key areas to consider, isolation from
digital noise and noise coupling between the transmitter and
receiver.
Filtering for the
ICS1890
is accomplished by separating the
power supply into three domains: digital, transmit, and receive.
All supply pins on the device fall into one of these three
categories as shown in the table below.
In the above table, each supply pin is followed directly by its
ground pin. Each supply pair should be bypassed with a 0.1µF
capacitor located as close to the device as possible.
The PCB board may have separate power and ground planes
for the
ICS1890
. The power planes could be split into three
domains following the pin isolation. A single, uniform plane
should be used for ground. Power plane placement is illustrated
in the figure below.
Point-to-point trace routing for power connections may be
used instead of actual power planes if required by printed
circuit board constraints.
Both the Receive and Transmit Domains should be connected
to the Digital Domain or main supply through a ferrite bead or
inductor, with a value of .1µH to 1µH. The best filter configuration
is a pi filter composed of a .1µH capacitor, .1µH ferrite bead,
and a .1µH capacitor at the device pin.
Reserved & N/C Pins
Four pins are labeled Reserved or N/C. These pins should
be left unconnected. Connecting these pins to ground or
power may prevent the device from operating properly
Digital Domain
Transmit Domain
Receive Domain
41 VDD 8 VDD
40 VSS 7VSS
16 VDD
18 VDD
17 VSS
54 VDD
51 VSS
56 VDD
55 VSS
25 VDD
29 VSS
57 VDD
63 VSS
Summary of Contents for PHYceiver ICS1890
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