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ICS1890
100M Stream Interface
100M Stream Interface - Pin Mapping
When the
ICS1890
is operating in the stream mode, the MII
Data Interface is remapped to accommodate the 100M Stream
Interface. The following table details the exact pin mapping.
Each individual pin description also contains the new 100M
Stream Interface pseudo pin name followed by the real MII
Data Interface pin name that it is mapped onto.
100M Stream Interface provides a lower latency parallel
interface producing an AMD PDR/PDT and twister type 5 bit
unscrambled interface when the data is scrambled by the
upper layer.
MII
Stream
TXCLK
STCLK
TXEN
(1)
TXER
STD4
TXD3
STD3
TXD2
STD2
TXD1
STD1
TXD0
STD0
RXCLK
SRCLK
RXDV
(2)
RXER
SRD4
RXD3
SRD3
RXD2
SRD2
RXD1
SRD1
RXD0
SRD0
CRS
SCRS
COL
(3)
LSTA
SD
Summary of Contents for PHYceiver ICS1890
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