IBT Technologies CI7BM, User Manual

Page: 55 / 113

Chapter 3 BIOS Configuration
CI7BM User’s Manual 51
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH is
cached, provided that the cache controller is disabled.
Video RAM Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a memory access error may result.
8 Bit I/O Recovery Time
This option specifies the length of the delay (in sysclks) inserted between
consecutive 8-bit I/O operations. The settings are 1, 2, 3, 4, 5, 6, 7, or 8.
The default setting is
3 .
16 Bit I/O Recovery Time
This option specifies the length of the delay (in sysclks) inserted between
consecutive 16-bit I/O operations. The settings are 1, 2, 3, 4, 5, 6, 7, or 8.
The default setting is
2 .
Memory Hole at 15MB - 16MB
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory from
15MB and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to
Disabled .
Passive Release
When enabled, CPU to PCI bus accesses are allowed during passive
release. Otherwise, the arbiter only accepts another PCI master access to
local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select
Enabled to support compliance with PCI
specification version 2.1. The default setting is Enabled .
CPU Warning Temperature
This field sets the threshold temperature at which an alert is sounded
through the system’s speaker. The CPU temperature is monitored by the
onboard thermal sensor to prevent the CPU from overheating.