IBT Technologies CI7BM, User Manual

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Chapter 3 BIOS Configuration
50 CI7BM User’s Manual
DRAM Clock
The DRAM Clock can be set to Host CLK or the CPU clock itself and to
66MHz . By default, this field is set to Host CLK .
SDRAM Precharge Control
This field enables of enables the SDRAM Precharge Control.
SDRAM Cycle Length
This field sets the SDRAM cycle length to either 2 or 3. The default
setting is
3 .
Memory Hole
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory from
15MB and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to
Disabled.
Read Around Write
DRAM optimization feature: If a memory read is addressed to a location
whose latest write is being held in a buffer before being written to
memory, the read is satisfied through the buffer contents, and the read is
not sent to the DRAM. The default setting is
Enabled .
Concurrent PCI/Host
This field enables or disables the concurrent PCI/Host. The default
setting is
Disabled .
Video RAM Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a memory access error may result.
DRAM Data Integrity Mode
Set this field to ECC if the DRAM installed in the system supports it.
Otherwise, do not reset the default of Non-ECC .
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH is cached, provided that the cache controller is
disabled.