IBT Technologies CI7BM, User Manual

Page: 53 / 113

Chapter 3 BIOS Configuration
CI7BM User’s Manual 49
Chipset Features Setup
This Setup menu controls the configuration of the chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
SDRAM RAS-to-CAS Delay :
3
CPU Warning Temperature : 66
°
C/151
°
F
SDRAM RAS Precharge Time
:
3 Current System Temp. :
SDRAM CAS Latency Timer
:
3 Current CPU Temperature :
SDRAM Precharge Control
:
Disabled CPU Fan Speed :
DRAM Data Integrity Mode : Non-ECC Chassis Fan Speed :
System BIOS Cacheable : Disabled VCCP (V): 1.98 V VTT (V) : 1.50 V
Video BIOS Cacheable : Enabled VCC3 (V) : 3.45 V + 5 V : 4.99 V
Video RAM Cacheable : Di12 V : 12.46 V -12 V : -12.54V
8 Bit I/O Recovery Time : 3 -5V : - 5.21 V
16 Bit I/O Recovery Time : 2 Shutdown Temperature : 75
°
C/167
°
F
Memory Hole At 15MB-16MB : Disabled
Passive Release : Enabled
Delayed Transaction : Disabled
ESC : Quit
Ç È Æ Å
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
SDRAM RAS-to-CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Stove (RAS) to Column Address Strobe (CAS).
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
Bank DRAM Timing
These fields define the speed of the DRAM memory onboard. The
options are
Normal , Medium , Fast , Turbo , SDRAM 8ns and
SDRAM10ns . By default, these fields are set to SDRAM 10ns .