IBM Ultrastar 36LZX Specifications Download

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hard read error. ARRE and AWRE bits in Mode Page 1 do not affect ARHES operation and ARHES
works independently.

ASDPE

(Additional Save Data Pointer Enable) bit is used to control the sending of additional save

data pointers messages. When set it will cause a save data pointers message to be sent on every
disconnection. This bit is only used by the Target after the Default Mode parameter values are over-
ridden with the Saved values which are read from the Reserved Area of the media as a part of the
motor startup sequence. Before the Saved values are read from the Reserved Area of the media,
the Save Data Pointer message is always sent to the Initiator prior to disconnection. When not set, a
save data pointers message is sent only if the current connection contained a data phase and a
further data phase will be required to complete the command.

CMDAC

(Command Active) bit in conjunction with

LED Mode

bits determines if an LED on the drive

is activated while commands are active. If CMDAC bit is one and LED Mode bits are zero, an LED
driver is active when a command is queued or executed.

RRNDE

(Report Recovered Non Data Errors) bit controls the reporting of recovered Non Data Errors

when the PER bit is set. If RRNDE is set, recovered Non Data Errors are reported. If the RRNDE bit
is not set, then recovered Non Data Errors are not reported.

CPE

(Concurrent Processing Enable) bit is allowed to be modified by the initiator for host system

device driver compatibility. Read(6), Read extend(10), Write(6), Write extend(10), and untagged and
unlinked Request Sense or Inquiry can be executed concurrently in both CPE bit set to 0 and 1.

FDD

(Format Degraded Disable) bit of 1 prevents the drive from reporting Format degraded. An FDD

bit of 0 indicates that Format degraded is reported for the Test Unit Ready Command and causes
media access commands (i.e. Read, Write) to report a media error if degraded.

CAEN

When set this bit causes the Command Age Limit timer to be used to avoid commands

waiting in the command queue for an indefinite period. When commands have been in the queue for
a period of time greater than the timer limit they will be reordered to be executed on a first come first
served basis. When this bit is reset, commands are always executed based on the queue reordering
rules.

IGRA

(Ignore Reassigned LBA) bit is set to 1 for preventing the drive from reassigned processing

against reassigned LBA when RC bit (Mode Page 1 byte 2 bit 4) is active. The main purpose of this
bit is to avoid undesirable read processing time delay due to reassigned LBA processing for contin-
uous data availability requirements such as Audio Visual application. IGRA bit set to 0 specifies that
the drive shall process reassigned LBA even if RC bit is active.

AVERP

(AV ERP Mode) bit is set to one in order to specify maximum retry counts during DRP and

command execution time limit. When AVERP bit is set to one, the maximum retry counts for read
and write operations are specified by Read Retry Count (Mode Page 1 Byte 3) and Write Retry
Count (Mode Page 1 Byte 8) respectively. Recovery Time Limit (Mode Page 1 Byte 10 and 11) is
effective to limit the command execution time. AVERP bit is set to zero to ignore the Recovery Time
Limit value and to specify that the drive shall process DRP up to the default maximum retry count
when Read Retry Count and Write Retry Count are set to a non-zero value.

EQuiet

(Enable Quiet), when set, enables Quiet Seek Mode for better acoustic performance.

ADC

(Adaptive Cache Enable), when set, allows the drive to modify the read-ahead caching

algorithm, ignoring parameters in Page 8. The adaptation is based on analyzing the most recent
command history and the current contents of the cache buffers.

Ultrastar 36LZX hard disk drive specifications