IBM RS/6000 SP, Problem Determination Manual

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4.3.3 HiPS Clock Subsystem
Understanding the switch clock subsystem will help you to get a better
appreciation of how various failures in the clock tree could cause certain
patterns of errors to arise in the log files.
• The HiPS clock subsystem
The clock subsystem is divided in two parts: (1) The clock card and (2) The
switch card. The clock card has an onboard oscillator and three inputs
coming from the switch card data connectors that correspond to J3, J5, and
J7 of the bulkhead. It redrives the selection of one of those four inputs. The
redrive destination is the HiPS 3.0 card. There are also some redrives to J1
and J2 on the clock card. These were used by HiPS 2.0 switches (which, as
you recall, have external clock cables), rather than embedded in the data
cables.
Figure 49. The HiPS Clock Subsystem
The clock is driven from the clock card selection logic to the switch card.
From there, it is redriven to two major branches: one drives the data cables
and the other drives the switch chips.
Each data cable has a clock put on pins 37 and 38. The cable twists these to
the input pins 13 and 14 on the other side.
Of course, as mentioned earlier, only J3, J5, and J7 on the switch are used
for the inputs, and each node gets a copy of the clock. The clocks that do
not end up at nodes or at J3, J5, or J7 are terminated at the connector that
receives them; there is a 100 ohm resistor across pins 13 and 14 of the data
connector.
You can see how these are redriven by looking at the third part of the
picture. From the clock card you have a branch at level A, which is divided
into four branches in level B. Each branch is driven by a different redrive
chip. Note that the odd jacks J3 to J17 are on one branch, while the odd
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