Honeywell
COMPONENT MAINTENANCE MANUAL
PART NUMBER 964-0452
1I.B.1516A Page 54
Mar 30/01
23-12-01
A minimum interval of 4 bits is defined between 2 ARINC words.
Minimum Interval between two ARINC Words
Figure 28
The bit rate is 12.5kbit/s. A TTL high pulse is obtained separately for a logical 0
and a logical 1 from the inverted and noninverted lines via 2 comparators at
each ARINC input circuit.
Assignment of ARINC Level to TTL Level
Figure 29
The 2 TTL signals are now logically linked by an OR gate, thus providing the re-
ceive pulse for the 32-bit shift register.
The data for the shift register are obtained by applying the noninverted line to
the SET input and the inverted line to the RESET line of an RS flip-flop.
This signal diagram results:
Linking Diagram of TTL Signals
Figure 30
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