Honeywell
COMPONENT MAINTENANCE MANUAL
PART NUMBER 964-0452
I.B.1516A Page 25
Mar 30/01
23-12-01
5
Loop 3
The frequency for the 1st mixer (1. OSC), which can vary between 42025kHz
and 70024.9kHz in increments of 100Hz, is generated in loop 3. The VCO of this
loop is synchronized to the sum of the output frequency of loop 2 and the output
frequency of the DDS. Ref. Fig. 10 for block diagram.
The VCO, with transistor, V35, is set up in exactly the same way as the VCO of
loop 2. Presetting is also effected according to Fig. 11. The output signal of the
VCO is supplied to the 2 base stages, V27 and V29, via impedance transformer
V36. V27 produces a level of about +4dBm to drive the oscillator amplifier of the
1st mixer in the receive and transmit path. The difference frequency between
the VCO of loop 3 and loop 2 is formed in mixer U42 (MIX), and is supplied to
phase comparator A13D1, following amplification in A13V20 and A13Vl5.
The output signal of the DDS is applied at the other input of the phase compar-
ator. A phase difference between these 2 signals causes a change in the control
voltage (UR3) after integrator A13N1-A and amplifier A13N1-B, which subse-
quently readjusts the VCO to its nominal frequency.
The time constant of the loop filter is switched over with the DATA signal. Phase
distortion can be corrected more effectively with data traffic, owing to the larger
bandwidth; the signal-to-noise ratio is better with voice communication, owing
to the small bandwidth.
Some frequency changes may result in the frequency of the VCO being too low
after the change by more than twice the frequency of the DDS. In such cases,
the loop fails to lock (image!), but instead goes to the lower limit of the control
voltage. The output of the phase comparator is on LOW. In this case, A13.N1-C
switches to HIGH after about 1ms, and locking aid A13N1-D generates a pulse
that brings the loop out of the image frequency so that the loop locks correctly.
6
CM monitoring
All 3 loops have 1 output in their phase comparator that is HIGH primarily only
with the Loop Locked. These data are summed with a monitor of the transmit
operation by diodes in point LOC-DET and supplied to comparator A13N2-B. In
the event of a loop failure, the comparator output switches to HIGH, and this in-
formation is transferred to the signal processor via inverter A13D2-A. The
CM-INHIBIT signal prevents CM fault messages with frequency changes. Any
change to the CM state triggers a CM interrupt via A13D2-B.
(b)
Receive section
The incoming signals in the range from 2.0000 to 29.9999MHz are received at the
RF antenna input of Receiver/Exciter, A1. They are converted to the intermediate
frequencies 40.025MHz and 25kHz. The 25kHz signal undergoes digital conversion
in an A/D converter and is further processed in a signal processor.
Receivers/Exciters, A1, has 3 600
Ω
outputs:
– Audio output, adjustable -20 to +I0dBm
– Data output 0dBm
– SELCAL output 500mV
Refer to the block diagrams in Figs. 14 and 15.
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