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HT66FM5440
Brushless DC Motor A/D Flash MCU
HT66FM5440
Brushless DC Motor A/D Flash MCU
UART Transmitter
Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1
register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which
is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the
Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the
transmit data register, which is known as the TXR_RXR register. The data to be transmitted is loaded
into this TXR_RXR register by the application program. The TSR register is not written to with new
data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has
been transmitted, the TSR can then be loaded with new data from the TXR_RXR register, if it is
available. It should be noted that the TSR register, unlike many other registers, is not directly mapped
into the Data Memory area and as such is not available to the application program for direct read/write
operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but
the data will not be transmitted until the TXR_RXR register has been loaded with data and the baud
rate generator has defined a shift clock source. However, the transmission can also be initiated by first
loading data into the TXR_RXR register, after which the TXEN bit can be set. When a transmission of
data begins, the TSR is normally empty, in which case a transfer to the TXR_RXR register will result
in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission
will immediately cease and the transmitter will be reset. The TX output pin can then be configured as
the I/O or other pin-shared functions by configuring the corresponding pin-shared control bits.
Transmitting Data
When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with
the least significant bit first. In the transmit mode, the TXR_RXR register forms a buffer between
the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been
selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a
data transfer can be summarized as follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin.
• Access the USR register and write the data that is to be transmitted into the TXR_RXR register.
Note that this step will clear the TXIF bit.
This sequence of events can now be repeated to send additional data.
It should be noted that when TXIF=0, data will be inhibited from being written to the TXR_RXR
register. Clearing the TXIF flag is always achieved using the following software sequence:
1. A USR register access
2. A TXR_RXR register write execution
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR_RXR
register is empty and that other data can now be written into the TXR_RXR register without
overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt.
During a data transmission, a write instruction to the TXR_RXR register will place the data into the
TXR_RXR register, which will be copied to the shift register at the end of the present transmission.
When there is no data transmission in progress, a write instruction to the TXR_RXR register will
place the data directly into the shift register, resulting in the commencement of data transmission,
and the TXIF bit being immediately set. When a frame transmission is complete, which happens
after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the
following software sequence is used:
1. A USR register access
2. A TXR_RXR register write execution
Note that both the TXIF and TIDLE bits are cleared by the same software sequence.