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Holtek HT66FM5440, Manual

The Holtek HT66FM5440 is a versatile product that offers a wide range of features. With its user-friendly interface, obtaining the manual for this device has never been easier. You can freely download the comprehensive manual from our website, ensuring a seamless experience with your HT66FM5440.

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HT66FM5440

Brushless DC Motor A/D Flash MCU

HT66FM5440

Brushless DC Motor A/D Flash MCU

UCR2 Register

The UCR2 register is the second of the two UART control registers and serves several purposes. One 
of its main functions is to control the basic enable/disable operation of the UART Transmitter and 
Receiver as well as enabling the various UART interrupt sources. The register also serves to control 
the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on 
each of the bits is given below:

Bit

7

6

5

4

3

2

1

0

Name

TXEN

RXEN

BRGH

ADDEN

WAKE

RIE

TIIE

TEIE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7

 TXEN

: UART Transmitter enabled control

0: UART transmitter is disabled

1: UART transmitter is enabled

The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to "0", the 

transmitter will be disabled with any pending data transmissions being aborted. In 

addition the buffers will be reset. In this situation the TX pin will be set in a floating 

state. 
If the TXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the 

transmitter will be enabled and the TX pin will be controlled by the UART. Clearing 

the TXEN bit during a transmission will cause the data transmission to be aborted and 

will reset the transmitter. If this situation occurs, the TX pin will be set in a floating 

state.

Bit 6

 RXEN

: UART Receiver enabled control

0: UART receiver is disabled

1: UART receiver is enabled

The bit named RXEN is the Receiver Enable Bit. When this bit is equal to "0", the 

receiver will be disabled with any pending data receptions being aborted. In addition 

the receive buffers will be reset. In this situation the RX pin will be set in a floating 

state. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the 

receiver will be enabled and the RX pin will be controlled by the UART. Clearing the 

RXEN bit during a reception will cause the data reception to be aborted and will reset 

the receiver. If this situation occurs, the RX pin will be set in a floating state.

Bit 5

 BRGH

: Baud Rate speed selection

0: Low speed baud rate

1: High speed baud rate

The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. 

This bit, together with the value placed in the baud rate register BRG, controls the 

Baud Rate of the UART. If this bit is equal to "1", the high speed mode is selected. If 

the bit is equal to "0", the low speed mode is selected.

Bit 4

 ADDEN

: Address detect function enable control

0: Address detect function is disabled

1: Address detect function is enabled

The bit named ADDEN is the address detect function enable control bit. When this 

bit is equal to "1", the address detect function is enabled. When it occurs, if the 8th 

bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if 

BNO=1, has a value of "1", then the received word will be identified as an address, 

rather than data. If the corresponding interrupt is enabled, an interrupt request will be 

generated each time the received word has the address bit set, which is the 8th or 9th 

bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the 

received word is "0" with the address detect function being enabled, an interrupt will 

not be generated and the received data will be discarded.

Summary of Contents for HT66FM5440

Page 1: ...Brushless DC Motor A D Flash MCU HT66FM5440 Revision V1 00 Date June 28 2017 ...

Page 2: ...ifier 1 2 Electrical Characteristics 17 Unit Gain Buffer Electrical Characteristics 17 Comparators Electrical Characteristics 18 Power on Reset Characteristics 18 System Architecture 19 Clocking and Pipelining 19 Program Counter 20 Stack 20 Arithmetic and Logic Unit ALU 21 Flash Program Memory 22 Structure 22 Special Vectors 22 Look up Table 22 Table Program Example 23 In Circuit Programming ICP 2...

Page 3: ... Considerations 38 Wake up 39 Watchdog Timer 40 Watchdog Timer Clock Source 40 Watchdog Timer Control Register 40 Watchdog Timer Operation 41 Reset and Initialisation 42 Reset Functions 42 Reset Initial Conditions 44 Input Output Ports 51 Pull high Resistors 52 Port A Wake up 52 I O Port Control Registers 53 Pin shared Functions 53 I O Pin Structures 60 Programming Considerations 60 Timer Modules ...

Page 4: ...ator Register 110 Over Current Detection 111 Over Current Detect Functional Description 111 Over Current Detect Register 112 Phase Current Detection 113 Phase Current Detect Functional Description 113 Phase Current Detect Register 113 BLDC Motor Control Circuit 114 Functional Description 114 PWM Counter Control Circuit 115 Mask Function 119 Other Functions 124 Hall Sensor Decoder 126 Motor Protect...

Page 5: ...onfiguration 178 Interrupt Preempt Function 180 Interrupt Operation 181 Hall Sensor Interrupts 184 External Interrupt 1 184 Noise Filter Input Interrupt 185 Comparator Interrupt 185 CAPTM Interrupts 185 Multi function Interrupts 186 PWM Module Interrupts 186 A D Converter Interrupts 187 TM Interrupts 187 UART Interrupt 188 I2 C Interrupt 188 Time Base Interrupt 188 LVD Interrupt 189 Interrupt Wake...

Page 6: ...anches and Control Transfer 195 Bit Operations 195 Table Read Operations 195 Other Operations 195 Instruction Set Summary 196 Table Conventions 196 Extended Instruction Set 198 Instruction Definition 200 Extended Instruction Definition 209 Package Information 216 28 pin SSOP 150mil Outline Dimensions 217 ...

Page 7: ... measurement input capture compare match output or PWM output or single pulse output function Single 16 bit CAPTM for motor protection 3 channel 10 bit PWM with complementary outputs for BLDC application 6 external channels 10 12 bit resolution A D converter Normal A D conversion Delay auto triggered A D conversion up to 4 channels available for each conversion I2 C Interface Single Fully duplex U...

Page 8: ...eriod or duty signal to trigger the A D conversion If using the interrupt to check for the end of the A D conversion the main program or subroutine program running will not be affected during the conversion process With the A D auto scan continuous sampling function provided the A D converter also supports 10 bit or 12 bit resolution which is adjustable according to the actual resolution and sampl...

Page 9: ... GCT GCB H1 H2 H3 C1P C3P C1N C3N Pin Shared With Port B OPA1N OPA1O OPA2P OPA2N OPA2O CMP0 Analog Peripherals AVDD VSS AVSS CAPTM 8 16 bit MDUs Pin Assignment PA6 OPA1O C1N AN PA OPA O NFIN AN6 PD0 TP0_0 TCK0 OPA1N AN0 PD1 TP0_1 OPA1P AN1 VSS AVSS VDD AVDD PA1 TCK AP AN3 PD TP1_0 INT1 OPA N PD3 TP1_1 OPA P PB1 CTIN HBO SCL PB TP3_1 HCO SDA PB0 INT1 NFIN TP3_0 HAO TCK3 PC0 GAT PC1 GAB PA5 C3P H3 P...

Page 10: ...APS0 ST CMOS General purpose I O Register enabled pull up and wake up SCL PAPS0 PRM ST I2 C clock line TX PAPS0 PRM CMOS External UART TX serial data output pin ICPCK ST ICP clock pin OCDSCK ST OCDS clock pin for EV chip only PA3 C1P H1 TCK1 PA3 PAPU PAWU PAPS0 ST CMOS General purpose I O Register enabled pull up and wake up C1P PAPS0 AN Comparator 1 positive intput H1 PAPS0 ST Hall sensor input T...

Page 11: ...OS Test pin for SB SCL PBPS0 PRM ST I2 C clock line PB2 TP3_1 HCO SDA PB2 PBPU PBPS0 ST CMOS General purpose I O Register enabled pull up TP3_1 PBPS0 CMOS PTM3 output HCO PBPS0 CMOS Test pin for SC SDA PBPS0 PRM ST NMOS I2 C data address line PB3 C1N CPN PB3 PBPU PBPS0 ST CMOS General purpose I O Register enabled pull up C1N PBPS0 PRM AN Comparator 1 negative input CPN PBPS0 AN Comparator 1 2 3 ne...

Page 12: ...T PCPS1 CMOS Pulse width modulation complementary output PC5 GCB PC5 PCPU PCPS1 ST CMOS General purpose I O Register enabled pull up GCB PCPS1 CMOS Pulse width modulation complementary output PD0 TP0_0 TCK0 OPA1N AN0 PD0 PDPU PDPS0 ST CMOS General purpose I O Register enabled pull up TP0_0 PDPS0 ST CMOS PTM0 input ouput TCK0 PDPS0 ST PTM0 clock input OPA1N PDPS0 AN Operational Amplifier 1 negative...

Page 13: ...m Ratings may cause substantial damage to the device Functional operation of the device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability D C Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage HIRC fSYS 16MHz 4 5 5 5 V IDD Operating Curren...

Page 14: ... External Interrupt Minimum Pulse Width 1 5 10 tSYS tSST System Start up Timer Period Wake up from HALT Status fSYS fHIRC 15 16 tSYS tRSTD System Reset Delay Time Power on Reset 25 50 100 ms System Reset Delay Time Any Reset except Power On Reset 8 3 16 7 33 3 ms Note 1 tSYS 1 fSYS 2 To maintain the accuracy of the internal HIRC oscillator frequency a 0 1μF decoupling capacitor should be connected...

Page 15: ...ential Non linearity 4 5V VREF AVDD VDD tADCK 0 1μs 10 bit 3 3 LSB 5 5V 4 5V VREF AVDD VDD tADCK 10μs 10 bit 5 5V 4 5V VREF AVDD VDD tADCK 0 16μs 12 bit 3 3 LSB 5 5V 4 5V VREF AVDD VDD tADCK 10μs 12 bit 5 5V INL A D Integral Non linearity 4 5V VREF AVDD VDD tADCK 0 1μs 10 bit 4 4 LSB 5 5V 4 5V VREF AVDD VDD tADCK 10μs 10 bit 5 5V 4 5V VREF AVDD VDD tADCK 0 16μs 12 bit 4 4 LSB 5 5V 4 5V VREF AVDD V...

Page 16: ...est Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage VLVR 5 5 5 V IPD Power Down Current 5V 0 1 μA VOPOS Input Offset Voltage 5V Without calibration A0OF 4 0 10000B 15 15 mV 5V With calibration 2 2 VCM Common Mode Voltage Range 5V VSS VDD 1 4 V VOR Maximum Output Voltage Range 5V VSS 0 2 VDD 0 2 V IOP Operating Current 5V 300 μA PSRR Power Supply Rejection Ratio 5V 90 96 dB CMRR Co...

Page 17: ...s GBW Gain Band Width 5V RL 100kΩ CL 100pF 1 MHz AOL Open Loop Gain 5V RL 100kΩ CL 100pF 60 80 dB PM Phase Margin 5V RL 100kΩ CL 100pF 50 60 Unit Gain Buffer Electrical Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage VLVR 5 5 5 V IPD Power Down Current 5V 0 1 μA VOPS Input Offset Voltage 5V Without calibration 15 15 mV VCM Common Mode ...

Page 18: ...0 30 50 mV VCM Input Common Mode Voltage Range VSS VDD 1 4 V AOL Comparator Open Loop Gain 100 120 dB tPD Comparator Response Time 5V VCM 0 VDD 1 4V With 10mV overdrive 1 μs 5V With 100mV overdrive Note 200 ns Note Measured with comparator one input pin at VCM VDD 1 4 2 while the other pin input transition from VSS to VCM 100mV or from VDD to VCM 100mV Power on Reset Characteristics Ta 25 C Symbol...

Page 19: ...ost high volume production for controller applications Clocking and Pipelining The main system clock derived from the HIRC oscillator is also used as the instruction clock The Program Counter is incremented at the beginning of the the system clock during which time a new instruction is fetched The following two system clocks carry out the instruction decoding execution and the data write back func...

Page 20: ...only this low byte is available for manipulation the jumps are limited to the present page of memory that is 256 locations When such program jumps are executed it should also be noted that a dummy cycle will be inserted Manipulating the PCL register may cause program branching so an extra cycle is needed to pre fetch Stack This is a special part of the memory which is used to save the contents of ...

Page 21: ... required arithmetic or logical operations after which the result will be placed in the specified register As these ALU calculation or operations may result in carry borrow or other status changes the status register will be correspondingly updated to reflect these changes The ALU supports the following functions Arithmetic operations ADD ADDM ADC ADCM SUB SUBM SBC SBCM DAA LADD LADDM LADC LADCM L...

Page 22: ...or the reset and interrupts The location 000H is reserved for use by the device reset for program initialisation After a device reset is initiated the program will jump to this location and begin execution Look up Table Any location within the Program Memory can be defined as a look up table where programmers can store fixed data To use the look up table the table pointer must first be setup by pl...

Page 23: ... be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions If using the table read instructions the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine As a rule it is recommended that simultaneous use of the table read instructions should be avoided However in situati...

Page 24: ...CU Programming Pins Pin Description ICPDA PA0 Programming Serial Data Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in circuit using this 4 wire interface Data is downloaded and uploaded serially on a single pin with an additional line for the clock Two additional lines are required for the power supply and one line for the re...

Page 25: ...D VDD Power Supply VSS VSS Ground Data Memory The Data Memory is a volatile area of 8 bit wide RAM internal memory and is the location where temporary information is stored Categorized into two types the first of these is an area of RAM known as the Special Function Data Memory These registers have fixed locations and are necessary for correct operation of the device Many of these registers can be...

Page 26: ...d instructions is that the data memory address m in the extended instructions has 10 valid bits for this device the high byte indicates a sector and the low byte indicates a specific address General Purpose Data Memory All microcontroller programs require an area of read write memory where temporary data can be stored and retrieved for use later It is this area of RAM memory that is known as Gener...

Page 27: ...A PAC CAPTC0 CAPTMAL CAPTMAH CAPTMCL CAPTMCH ADLVDL ADLVDH ADRL ADRH ADCR0 ADCR1 ADCR2 ADISG1 ADISG2 ADDL Sector 1 Pri_name4 Pri_name5 Pri_name6 Pri_name7 MFI3 MFI5 MFI6 MFI4 ADLVDH MFI7 IAR2 MP2L MP2H SMOD LVRC WDTC LVDC TBC Pri_name0 Pri_name1 Pri_name2 Pri_name3 STATUS PTM1C2 PB PBC PTM2C2 PC PCC PTM3C2 PD PDC PTM0BL ISRL0 ISRH0 ISRL1 ISRH1 ISRL2 ISRH2 ISRL3 ISRH3 ADLVDL Sector 0 2 MCD DTS PLC ...

Page 28: ...ng to the registers will result in no operation Memory Pointers MP0 MP1L MP1H MP2L MP2H Five Memory Pointers known as MP0 MP1L MP1H MP2L MP2H are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing...

Page 29: ...m data to acc lsub a m 1 compare m and m 1 data snz c m m 1 jmp continue no lmov a m yes exchange m and m 1 data mov temp a lmov a m 1 lmov m a mov a temp lmov m 1 a continue Note Here m is a data memory address located in any data memory sectors For example m 1F0H it indicates address 0F0H in Sector 1 Accumulator ACC The Accumulator is central to the operation of any microcontroller and is closel...

Page 30: ...ord the status and operation of the microcontroller With the exception of the TO and PDF flags bits in the status register can be altered by instructions like most other registers Any data written into the status register will not change the TO or PDF flag In addition operations related to the status register may give different results due to the different instruction operations The TO flag can be...

Page 31: ...e previous operation CZ flag and current operation zero flag For other instructions the CZ flag will not be affected Bit 5 TO Watchdog Time out flag 0 After power up or executing the CLR WDT or HALT instruction 1 A watchdog time out occurred Bit 4 PDF Power down flag 0 After power up or executing the CLR WDT instruction 1 By executing the HALT instruction Bit 3 OV Overflow flag 0 No overflow 1 An ...

Page 32: ... dynamically switching between different system clocks the device has the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Frequency Internal High Speed RC HIRC 16MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two oscillator sources one high speed oscillator and one low...

Page 33: ... System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks required for high performance will by their nature increase current consumption and of course vice versa lower speed clocks re...

Page 34: ... of operation for the microcontroller each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application The NORMAL Mode allows normal operation of the microcontroller The remaining three modes the SLEEP IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power Operating Mode Descr...

Page 35: ... driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer TMs and Time Base In the IDLE0 Mode the system oscillator will be stopped the fSUB fS and fTBC clocks will be on IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high In the IDLE1 Mo...

Page 36: ... is executed If this bit is high when a HALT instruction is executed the device will enter the IDLE Mode In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational if FSYSON bit is high If FSYSON bit is low the CPU and the system clock will all stop in IDLE0 mode If the bit is low the device will enter the SLEEP Mode when a HALT inst...

Page 37: ...when the device moves between the various operating modes NORMAL fSYS fH fH 64 fH on CPU run fSYS on fTBC on fSUB on IDLE0 HALT instruction executed CPU stop IDLEN 1 FSYSON 0 fSYS off fTBC on fSUB on IDLE1 HALT instruction executed CPU stop IDLEN 1 FSYSON 1 fSYS on fTBC on fSUB on SLEEP HALT instruction executed fSYS off CPU stop IDLEN 0 fTBC off fSUB on WDT or LVD on Entering the SLEEP Mode There...

Page 38: ...and registers will maintain their present condition The WDT will be cleared and resume counting The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as l...

Page 39: ...p that only resets the Program Counter and Stack Pointer the other flags remain in their original status Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system When a Port A pin wake up occurs the program will resume execution at the instruction following the HALT instruction If the system is woken up by an interrupt then two possib...

Page 40: ... controls the required timeout period as well as the enable operation The WDTC register is initiated to 01010011B at any reset and keeps unchanged at the WDT time out occurrence in a power down state WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function software control 01010 or 10101 Enable Other...

Page 41: ...If the WE4 WE0 bits are set to any other values other than 01010B and 10101B it will reset the device after 2 3 fLIRC clock cycles WE4 WE0 Bits WDT Function 01010B or 10101B Enable Any other value Reset MCU Watchdog Timer Enable Control Under normal program operation a Watchdog Timer time out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mod...

Page 42: ...begins execution from the first memory address a power on reset also ensures that certain other registers are preset to known conditions All the I O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs VDD Power on Reset SST Time out tRSTD Power on Reset Timing Chart Low Voltage Reset LVR The microcontroller contains a low voltage res...

Page 43: ... values above will also result in the generation of an MCU reset The reset operation will be activated after 2 3 fLIRC clock cycles However in this situation the register contents will be reset to the POR value CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 FSYSON fSYS Control in IDLE Mode Described elsewhere Bit 6 3 Unimplemented read as...

Page 44: ...y various microcontroller operations such as the SLEEP or IDLE Mode function or Watchdog Timer The reset flags are shown in the table TO PDF RESET Conditions 0 0 Power on reset u u LVR during NORMAL Mode operation 1 u WDT time out reset during NORMAL Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation u stands for unchanged The following table indicates the way in which the v...

Page 45: ... 0 1 0 1 0 0 11 uuuu uuuu INTEG1 0 0 0 0 0 0 0 0 0 0 0 0 INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuu uuuu INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu INTC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu INTC3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu MFI0 0 0 0 0 0 0 0 0 0 0 0 0 uuu uuu MFI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu MFI2 0 0 0 0 0 0 0 0 uu uu MFI3 0 0 0 0 0 0 0 0 uu uu MFI4 0 0 0 0 0 0 0...

Page 46: ... ADCRL_SEL 0 uuuu ADRFS 1 ADCRL_SEL 0 uuuu uuuu ADRFS 0 ADCRL_SEL 1 uu ADRFS 1 ADCRL_SEL 1 ADCR0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 uuuu uuuu ADCR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu ADCR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu u uu ADISG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu ADISG2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu ADDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu ADLVDL x x x x x x x x uuu...

Page 47: ...0 0 0 0 uuuu uuuu PTM0DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0AH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0RPH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PWMC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu DUTR0L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu DUTR0H 0 0 0 0 uu DUTR1L 0 0 0 0 0 0 0 ...

Page 48: ...x x x x x x x x x x x x x x x x x MDU1CTRL 0 0 0 0 uu NF_VIH 0 0 1 1 0 0 1 0 0 1 1 0 0 1 uu u uuuu NF_VIL 0 0 0 1 0 1 0 0 0 0 1 0 1 0 uu u uuuu TBC 0 0 1 1 0 0 1 1 uuuu Pri_name0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 uuuu uuuu Pri_ name1 0 1 0 0 0 0 11 0 1 0 0 0 0 11 uuuu uuuu Pri_ name2 0 11 0 0 1 0 1 0 11 0 0 1 0 1 uuuu uuuu Pri_ name3 1 0 0 0 0 111 1 0 0 0 0 111 uuuu uuuu Pri_ name4 1 0 1 0 1 0 0 1 1...

Page 49: ..._SEL 1 uuuu uuuu ADRFS 1 ADCRL_SEL 1 ISRH1 x x x x x x x x x x x x x x x x uuuu uuuu ADRFS 0 ADCRL_SEL 0 uuuu ADRFS 1 ADCRL_SEL 0 uuuu uuuu ADRFS 0 ADCRL_SEL 1 uu ADRFS 1 ADCRL_SEL 1 ISRL2 x x x x x x x x uuuu ADRFS 0 ADCRL_SEL 0 uuuu uuuu ADRFS 1 ADCRL_SEL 0 uu ADRFS 0 ADCRL_SEL 1 uuuu uuuu ADRFS 1 ADCRL_SEL 1 ISRH2 x x x x x x x x x x x x x x x x uuuu uuuu ADRFS 0 ADCRL_SEL 0 uuuu ADRFS 1 ADCRL_...

Page 50: ...0 0 0 0 0 0 0 0 u uuuu HNF_MSEL 0 0 0 0 0 0 0 0 uuuu PTM2C0 0 0 0 0 0 0 0 0 0 0 uuuu u PTM2C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM2DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM2DH 0 0 0 0 uu PTM2AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM2AH 0 0 0 0 uu PTM2RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM2RPH 0 0 0 0 uu HDCT0 0 0 0 0 0 0 0 0 0 0 0 0 uu uuuu HDCT1 0 0 0 0 0 0 0 0 0...

Page 51: ...o meet the needs of a wide range of application possibilities The device provides bidirectional input output lines labeled with port names PA PD These I O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table All of these I O ports can be used for input and output operations For input operation these ports are non latching which means the...

Page 52: ...Disable 1 Enable The PxPUn bit is used to control the pin pull high function Here the x can be A B C and D However the actual available bits for each I O Port may be different Port A Wake up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power a feature that is important for battery and other low power applications Various methods exist to wake up the m...

Page 53: ...lti function I O pins is selected by a series of registers via the application program control Pin shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain However by allowing the same pins to share several different functions and providing a means of function selection a wide range of diffe...

Page 54: ...6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 PBPS0 PB3S1 PB3S0 PB2S1 PB2S0 PB1S1 PB1S0 PB0S1 PB0S0 PBPS1 PB7S1 PB7S0 PB6S1 PB6S0 PB5S1 PB5S0 PB4S1 PB4S0 PCPS0 PC3S1 PC3S0 PC2S1 PC2S0 PC1S1 PC1S0 PC0S1 PC0S0 PCPS1 PC5S1 PC5S0 PC4S1 PC4S0 PDPS0 PD3S1 PD3S0 PD2S1 PD2S0 PD1S1 PD1S0 PD0S1 PD0S0 PRM NFINPS INT1PS RXPS TXPS C1NPS1 C1NPS0 SDAPS SCLPS Pin shared Function Selection Registers List PAPS0 Register Bit 7 ...

Page 55: ...ection 00 PA4 H2 01 PA4 H2 10 C2P 11 C1N PBPS0 Register Bit 7 6 5 4 3 2 1 0 Name PB3S1 PB3S0 PB2S1 PB2S0 PB1S1 PB1S0 PB0S1 PB0S0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PB3S1 PB3S0 PB3 Pin Shared function selection 00 PB3 01 C1N 10 CPN 11 PB3 When these bits are set to 10B the C1N C2N and C3N will be shorted internally and the CPN pin function is selected Refer to the Compa...

Page 56: ...Rev 1 00 56 June 28 2017 HT66FM5440 Brushless DC Motor A D Flash MCU 11 TP3_0 ...

Page 57: ...ction 00 PB6 01 RX 10 TP2_0 11 OPA0O Bit 3 2 PB5S1 PB5S0 PB5 Pin Shared function selection 00 PB5 01 TP2_1 10 C2N 11 PB5 Bit 1 0 PB4S1 PB4S0 PB4 Pin Shared function selection 00 PB4 01 TP2_0 10 C3N 11 PB4 PCPS0 Register Bit 7 6 5 4 3 2 1 0 Name PC3S1 PC3S0 PC2S1 PC2S0 PC1S1 PC1S0 PC0S1 PC0S0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PC3S1 PC3S0 PC3 Pin Shared function selecti...

Page 58: ...n 00 PC4 01 PC4 10 GCT 11 PC4 PDPS0 Register Bit 7 6 5 4 3 2 1 0 Name PD3S1 PD3S0 PD2S1 PD2S0 PD1S1 PD1S0 PD0S1 PD0S0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PD3S1 PD3S0 PD3 Pin Shared function selection 00 PD3 01 TP1_1 10 PD3 11 OPA2P Bit 5 4 PD2S1 PD2S0 PD2 Pin Shared function selection 00 PD2 INT1 01 TP1_0 10 PD2 INT1 11 OPA2N Bit 3 2 PD1S1 PD1S0 PD1 Pin Shared function ...

Page 59: ...it 7 NFINPS NFIN input source pin selection 0 PA7 1 PB0 Bit 6 INT1PS INT1 input source pin selection 0 PB0 1 PD2 Bit 5 RXPS RX input source pin selection 0 PB6 1 PA0 Bit 4 TXPS TX output source pin selection 0 PB7 1 PA2 Bit 3 2 C1NPS1 C1NPS0 C1N input source pin selection 00 PB3 01 PA4 10 PA6 11 Reserved Bit 1 SDAPS SDA input source pin selection 0 PA0 1 PB2 Bit 0 SCLPS SCL input source pin select...

Page 60: ...t to an input state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the port control registers are then programmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers are first programmed Selecting which pins are inputs and which are outputs can be achieved ...

Page 61: ... Channels 1 Single Pulse Output 1 PWM Alignment Edge PWM Adjustment Period Duty Duty or Period TM Function Summary PTM0 PTM1 PTM2 PTM3 16 bit PTM 16 bit PTM 10 bit PTM 10 bit PTM TM Name Type Reference TM Operation The different types of TM offer a diverse range of functions from simple timing operations to PWM signal generation The key to understanding how the TM operates is to see it in terms of...

Page 62: ...re the TM generates the PWM output waveform As the TM input and output pins are pin shared with other functions the TM input and output function must first be setup using relevant pin shared function selection bits described in the Pin shared Function section The TCKn and TPn_0 pins are also the capture input whose active edge can be a rising edge a falling edge or both rising and falling edges an...

Page 63: ...ng the following access procedures Accessing the CCRA CCRB or CCRP low byte registers without following these access procedures will result in unpredictable values Data B s bit B ffer PTMnDH PTMnDL PTMnAH PTMnBH PTMnAL PTMnBL PTMn Co nter Register Read only PTMn CCRA CCRB Register Read Write PTMnRPH PTMnRPL PTMn CCRP Register Read Write The following steps show the read and write procedures Writin...

Page 64: ...M0 PTIO1 PTIO0 TMnAF Interr pt TMnPF Interr pt PTPOL PTnIO1 PTnIO0 fSUB PTnCAPTS 000 001 010 011 100 101 110 111 b0 b15 b0 b15 0 1 1 0 CCRB PTnVLF Falling edge detect Rising edge detect Comparator P match only Comparator P match or TPn_0 TCKn rising edge Comparator P match or TPn_0 TCKn falling edge Comparator P match or TPn_0 TCKn d al edge PTnTCLR1 PTnTCLR0 00 01 10 11 TCKn TPn_1 CINS 1 0 Dat_O ...

Page 65: ... bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRA and CCRP comparators are 10 bit or 16 bit wide whose value is respectively compared with all counter bits The only way of changi...

Page 66: ...14 D13 D12 D11 D10 D9 D8 PTMnRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMnRPH D15 D14 D13 D12 D11 D10 D9 D8 16 bit Periodic TM Registers List n 0 1 Register Name Bit 7 6 5 4 3 2 1 0 PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR PTMnC2 PTnTCLR1 PTnTCLR0 PTnVLF PTMnDL D7 D6 D5 D4 D3 D2 D1 D0 PTMnDH D9 D8 PTMnAL D7 D6 D5 D4 D3 D2 D1 D0 PTMnAH D9 D8 PTMnBL ...

Page 67: ...er will retain its residual value until the bit returns high again If the PTMn is in the Compare Match Output Mode PWM output Mode or Single Pulse Output Mode then the PTMn output pin will be reset to its initial condition as specified by the PTnOC bit when the PTnON bit changes from low to high Bit 2 0 Unimplemented read as 0 PTMnC1 Register n 0 3 Bit 7 6 5 4 3 2 1 0 Name PTnM1 PTnM0 PTnIO1 PTnIO...

Page 68: ...IO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs After the PTMn output pin changes state it can be reset to its initial level by changing the level of the PTnON bit from low to high In the PWM Mode the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a ...

Page 69: ...PTnCCLR bit set high the counter will be cleared when a compare match occurs from the Comparator A When the bit is low the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero The PTnCCLR bit is not used in the PWM Mode Single Pulse or Capture Input Mo...

Page 70: ...W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 PTMn CCRA Low Byte Register bit 7 bit 0 PTMn 10 bit 16 bit CCRA bit 7 bit 0 PTMnAH Register n 0 1 Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D15 D8 PTMn CCRA High Byte Register bit 7 bit 0 PTMn 16 bit CCRA bit 15 bit 8 PTMnAH Register n 2 3 Bit 7 6 5 4 3 2 1 0 Name D9...

Page 71: ...n 10 bit CCRB bit 9 bit 8 PTMnRPL Register n 0 3 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 PTMn CCRP Low Byte Register bit 7 bit 0 PTMn 10 bit 16 bit CCRP bit 7 bit 0 PTMnRPH Register n 0 1 Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D15 D8 PTMn CC...

Page 72: ...rupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when PTnCCLR is high no TMnPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA can not be cleared to zero If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex or 16 bit FFFF Hex value however here t...

Page 73: ... PTnOC 0 Output Toggle with TMnAF flag Note PTnIO 1 0 10 Active High Output select Here PTnIO 1 0 11 Toggle Output select Output not affected by TMnAF flag Remains High until reset by PTnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTnPOL is high Compare Match Output Mode PTnCCLR 0 n 0 3 Note 1 With PTnCCLR 0 a Comparator P match will ...

Page 74: ...igh Output select Here PTnIO 1 0 11 Toggle Output select Output not affected by TMnAF flag Remains High until reset by PTnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTnPOL is high TMnPF not generated No TMnAF flag generated on CCRA overflow Output does not change Compare Match Output Mode PTnCCLR 1 n 0 3 Note 1 With PTnCCLR 1 a Compa...

Page 75: ... generated waveform is extremely flexible In the PWM Output Mode the PTnCCLR bit has no effect on the PWM operation Both of the CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle The PWM waveform frequency and duty cycle can therefore be co...

Page 76: ...t low Counter Reset when PTnON returns high PTnM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When PTnPOL 1 PWM Period set by CCRP PTMn O P Pin PTnOC 0 PWM Output Mode n 0 3 Note 1 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when PTnIO 1 0 00 or 01 4 The PTn...

Page 77: ...ding edge will be generated The PTnON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the...

Page 78: ...CRA Output Inverts when PTnPOL 1 No CCRP Interrupts generated PTMn O P Pin PTnOC 0 TCKn pin Software Trigger Cleared by CCRA match TCKn pin Trigger Auto set by TCKn pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Mode n 0 3 Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse is triggered by the TCKn pin or by setting the PTnON bit high 4 A TCKn pin acti...

Page 79: ...n the present value in the counter will be latched into the CCRA or CCRB registers and a PTMn interrupt generated Irrespective of what events occur on the TPn_0 or TCKn pin the counter will continue to free run until the PTnON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value...

Page 80: ...Rising edge 01 Falling edge 10 Both edges 11 Disable Capture XX YY XX YY Capture Input Mode PTnTCLR 1 0 00 n 0 3 Note 1 PTnM 1 0 01 PTnTCLR 1 0 00 and active edge set by the PTnIO 1 0 bits 2 A PTMn Capture input pin active edge transfers the counter value to CCRA 3 Comparator P match will clear the counter 4 PTnCCLR bit not used 5 No output function PTnOC and PTnPOL bits are not used 6 CCRP determ...

Page 81: ...e Resume Counter Reset Counter Stop CCRB Value XX PTnVLF YY XX Active edge Active edge XX Capture Input Mode PTnTCLR 1 0 01 n 0 3 Note 1 PTnM 1 0 01 PTnTCLR 1 0 01 and active edge set by the PTnIO 1 0 bits 2 A PTMn Capture input pin active edge transfers the counter value to CCRA or CCRB 3 Comparator P match or PTMn capture input pin rising edge will clear the counter 4 PTnCCLR bit is not used 5 N...

Page 82: ...e Pause Resume Counter Reset Counter Stop CCRB Value XX PTnVLF YY Active edge XX YY Capture Input Mode PTnTCLR 1 0 10 n 0 3 Note 1 PTnM 1 0 01 PTnTCLR 1 0 10 and active edge set by the PTnIO 1 0 bits 2 A PTMn Capture input pin active edge transfers the counter value to CCRA or CCRB 3 Comparator P match or PTMn capture input pin falling edge will clear the counter 4 PTnCCLR bit is not used 5 No out...

Page 83: ...ume Counter Reset Counter Stop CCRB Value XX PTnVLF YY XX Active edge Active edge XX Capture Input Mode PTnTCLR 1 0 11 n 0 3 Note 1 PTnM 1 0 01 PTnTCLR 1 0 11 and active edge set by the PTnIO 1 0 bits 2 A PTMn Capture input pin active edge transfers the counter value to CCRA or CCRB 3 Comparator P match or PTMn capture input pin rising or falling edge will clear the counter 4 PTnCCLR bit is not us...

Page 84: ...TM counter CAMCLR 1 CLR CapTM_Over CapTM_Cmp H1 H3 CAPS 1 0 16 bit CAPTM CLK CAPTCK 2 0 PWMO fSYS 2 fSYS 128 fSYS 64 INTA INTB INTC FHA FHB FHC H2 CTIN CAPEG 1 0 INTEG0 C3EN CMP 3 C2EN CMP 2 C1EN CMP 1 C3N C3P C2N C2P C1N C1P Hall Noise Filter HA HB HC HSEL CAPNFT CAPNFS CAPFIL HCHK_NUM HNF_MSEL Note The detailed control and input selection for the Hall noise filter is described in the Hall Sensor...

Page 85: ...rce for the CAPTM The clock source fH is the high speed system oscillator clock Bit 3 CAPTON CAPTM Counter On Off Control 0 Off 1 On This bit controls the overall on off function of the CAPTM Setting the bit high enables the counter to run clearing the bit disables the CAPTM Clearing this bit to zero will stop the counter from counting and turn off the CAPTM which will reduce its power consumption...

Page 86: ... the hardware will automatically transfer the value in the CAPTMDL and CAPTMDH register to the capture register pair CAPTMCL and CAPTMCH and then reset the CAPTM counter Bit 0 CAMCLR CAPTM Counter compare match auto reset control 0 Disable 1 Enable If this bit is set high when a compare match condition has occurred the hardware will automatically reset the CAPTM counter CAPTMDL Register Bit 7 6 5 ...

Page 87: ... can be used in Capture or Compare Mode There are four timer capture inputs FHA FHB FHC and CTIN Each of these capture inputs has its own edge detector selection it can be either a rising edge a falling edge or both rising and falling edges The CAPTON bit is used to control the overall Capture Timer enable disable function Disabling the Capture Module when not used will reduce the device power con...

Page 88: ...will be generated If the CAPCLR bit is set high then the 16 bit counter will be automatically reset after a capture event occurs Compare Mode Operation When the timer is used in the compare mode the CAPTMAL and CAPTMAH registers are used to store the 16 bit compare value When the free running value of the count up 16 bit counter reaches a value equal to the programmed values in these compare regis...

Page 89: ... outputs to the 16 bit PTM0 capture circuit in order to ensure that the motor control circuit works normally The noise filter circuit is an I O surge filtering analog circuit which can filter micro second grade sharp noise Antinoise pulse width maximum NF_VIH 4 0 NF_VIL 4 0 5μs NF_VIH 4 0 NF_VIL 4 0 1 CINS PT0CAPTS NF_BYPS Noise Filter 1 0 1 0 1 0 NFIN PD0 Data_Out Data_In Edge Detector PT0IO1 PT0...

Page 90: ...Noise Filter Dat_Out not selected remains original PTM0 capture path with 150ns filter 1 Noise Filter Dat_Out selected Bit 5 Unimplemented read as 0 Bit 4 0 D4 D0 NF_VIH register bit 4 bit 0 NF_VIL Register Bit 7 6 5 4 3 2 1 0 Name NFIS1 NFIS0 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W POR 0 0 0 1 0 1 0 Bit 7 6 NFIS1 NFIS0 NFIN interrupt edge control 00 Disable 01 Rising edge trigger 10 Fallin...

Page 91: ...e channel voltage to be measured However in this case the input voltage is limited in the range of VSS 0 1V to VDD 0 1V To convert a full voltage range of 0 VDD the external channel can be configured to bypass the unity gain buffer using the BYPSANn bit in the ADBYPS register The three internal channels which are OPA0 OPA1 and OPA2 outputs OPA0O OPA2O can not bypass the unity gain buffer when conn...

Page 92: ...A D converter low and high boundary values reapectively The ADDL register is used to determine the delay time between the DLSTR trigger action and the actual start of the A D conversion The remaining registers are control registers which setup the operating and control function of the A D converter Register Name Bit 7 6 5 4 3 2 1 0 ADRL ADRFS 0 ADCRL_SEL 0 D3 D2 D1 D0 ADRL ADRFS 1 ADCRL_SEL 0 D7 D...

Page 93: ...DRFS 0 ADCRL_SEL 0 D3 D2 D1 D0 ADHVDL ADRFS 1 ADCRL_SEL 0 D7 D6 D5 D4 D3 D2 D1 D0 ADHVDL ADRFS 0 ADCRL_SEL 1 D1 D0 ADHVDL ADRFS 1 ADCRL_SEL 1 D7 D6 D5 D4 D3 D2 D1 D0 ADHVDH ADRFS 0 ADCRL_SEL 0 D11 D10 D9 D8 D7 D6 D5 D4 ADHVDH ADRFS 1 ADCRL_SEL 0 D11 D10 D9 D8 ADHVDH ADRFS 0 ADCRL_SEL 1 D9 D8 D7 D6 D5 D4 D3 D2 ADHVDH ADRFS 1 ADCRL_SEL 1 D9 D8 ISRLn ADRFS 0 ADCRL_SEL 0 D3 D2 D1 D0 ISRLn ADRFS 1 ADCR...

Page 94: ...9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ADRFS ISRHn Read only ISRLn Read only 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note n 0 3 ADCRL_SEL 1 10 bit Format ADRFS ADRH Read only ADRL Read only 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 ...

Page 95: ...nversion status As the device contains only one actual analog to digital converter hardware circuit each of the external or internal analog signal inputs must be routed to the converter The ACS3 ACS0 bits in the ADCR0 register are used to determine which external or internal channel input is selected to be converted in the case of ADSTR triggered A D conversion In the case of auto scan triggered A...

Page 96: ...it should be cleared to zero to enable the A D converter If the bit is set high then the A D converter will be switched off reducing the device power consumption As the A D converter will consume a limited amount of power even when not executing a conversion this may be an important consideration in power sensitive battery powered applications It is recommended to set ADOFF bit high before enterin...

Page 97: ...ered A D conversion since it has a higher priority than the latter Bit 5 PWIS Select PWM source to trigger A D auto scan 0 Select PWM period to trigger auto scan 1 Select PWM duty to trigger auto scan When this bit is set high to select PWM duty to trigger auto scan conversion the detailed PWM duty source is furtherly determined by the PWDIS1 PWDIS0 bits in the ADCR2 register Bit 4 3 ADCHVE ADCLVE...

Page 98: ...ISn3 ADISn0 bits Bit 3 ISEOCB A D auto scan conversion finished flag 0 A D auto scan has not been triggered or A D auto scan has not finished 1 A D auto scan has been triggered and has finished When the A D auto scan has been triggered and all the selected channels have been converted this bit will be set high by hardware to indicate that the ISRLn ISRHn registers are available to read After the I...

Page 99: ...to the ADIS2 bit field defined channel While if it is the last channel the ISEOCB bit will be set high by hardware Then the A D converter will return to the channel selected by ACS bit field for use in ADSTR triggered conversions Bit 3 0 ADIS03 ADIS00 Auto scan triggered A D conversion first analog channel input selection 0000 AN0 0001 AN1 0010 AN2 0011 AN3 0100 OPA2 output 0101 OPA1 output 0110 O...

Page 100: ...B bit will be set high by hardware Then the A D converter will return to the channel selected by ACS bit field for use in ADSTR triggered conversions Bit 3 0 ADIS23 ADIS20 Auto scan triggered A D conversion third analog channel input selection 0000 AN0 0001 AN1 0010 AN2 0011 AN3 0100 OPA2 output 0101 OPA1 output 0110 OPA0 output 0111 AN6 1000 AN7 1001 1111 Undefined When using the auto scan mechni...

Page 101: ...gain buffer 1 Enable AN0 bypass unity gain buffer A D Converter Operation There are two ways to initiate an A D converter conversion cycle The first of these is to use the ADSTR bit in the ADCR0 register to start and reset the AD converter When the microcontroller sets this bit from low to high and then low again an analog to digital conversion cycle will be initiated When the ADSTR bit is brough ...

Page 102: ...e selected As the recommended range of permissible A D clock period tADCK is from 0 16μs to 10μs for 12 bit format and 0 1μs to 10μs for 10 bit format care must be taken for system clock frequencies Refer to the following table for examples where values marked with an asterisk show where special care must be taken as the values may exceed the specified A D Clock Period range fSYS A D Clock Period ...

Page 103: ... clock by correctly programming bits ADCK2 ADCK0 in the ADCR1 register Step 2 Enable the A D converter by clearing the ADOFF bit in the ADCR0 register to zero Step 3 Select which signal is to be connected to the internal A D converter by correctly configuring the ACS3 ACS0 bits in the ADCR0 register If external channel ANn is selected its bypass unity gain buffer function can be enabled or disable...

Page 104: ... registers Step 2 Select the required A D conversion clock by correctly programming bits ADCK2 ADCK0 in the ADCR1 register Select the PWM interrupt signal source by setting the PWIS bit and PWDIS1 PWDIS0 bits Select the number of channels to be converted by setting the ADCH_ SEL bit in the ADCR2 register And select which signals are to be orderly connected to the internal A D converter by correctl...

Page 105: ... for the end of the conversion process if the method of polling the ISEOCB bit in the ADCR2 register is used the interrupt enable step above can be omitted Considerations for simutaniously using both trigger methods ADSTR EOCB PWM Duty 3 trigger ADDL 3 ISEOCB 1 2 3 4 5 10 1234567 19 ADOFF 0 ACS 000 AN0 DLSTR 1 ADIS0 0110 OPA0 PWIS 1 PWDIS 11 PWM Duty 3 1 AN ch select by ACS AN0 ADC result will sav...

Page 106: ...has been finished the ISEOCB bit will be set high and the ISAEOCF interrupt will be generated When switching back to the ACS defined channel the converter will not re sample the interrupted A D conversion channel If users need to re sample the input channel set the ADSTR bit from low to high and low again Programming Considerations During microcontroller operations where the A D converter is not b...

Page 107: ...rsion is complete Example using an EOCB polling method to detect the end of conversion clr AEOCE disable A D interrupt mov a 03H mov ADCR1 a select fSYS 8 as A D clock clr ADOFF mov a 01h setup PDPS0 to configure pin AN0 mov PDPS0 a mov a 00h mov ADCR0 a enable and connect AN0 channel to A D converter start_conversion clr ADSTR high pulse on start bit to initiate conversion set ADSTR reset A D clr...

Page 108: ...rupt request flag set Int_prinF clear related interrupt priority request flag set AEOCE enable A D interrupt set Int_prinE enable related interrupt priority set EMI enable global interrupt A D interrupt service routine ADC_ISR mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a ADRL read low byte conversion result value mov ADRL_...

Page 109: ...N pin Comparators Block Diagram Comparator Operation The device contains four comparator functions which are used to compare two analog voltages and provide an output based on their difference Any pull high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled As the comparator inputs approach their switching level some spurious o...

Page 110: ...ol 0 Disable 1 Enable This is the comparator 1 hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator as specified in the Comparator Electrical Characteristics table The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold Bit 4 C0HYEN Comparator 0 hysteresis control 0 Disable 1 Enable This is the...

Page 111: ...f the comparator 0 is not used or before the device enters the SLEEP or IDLE mode Over Current Detection The device contains a fully integrated over current detect circuit which is used for motor protection OPCM Int_Is AP OPA0 Av 1 5 10 20 8 bit DAC OP Compare CKT Int_Is OPA0 CMP0 Int_AD_EOC or int_AD_ISEOC Int_AHL_ Lim ADC ADR ISR EOCB or ISEOCB AD HL LV Trigger Int_AHL_ Lim Int Trigger ADLVD ADH...

Page 112: ...ual edge trigger Bit 5 4 Unimplemented read as 0 Bit 2 0 OPA0VS2 OPA0VS0 OPA0 gain selection 000 OPA0 disabled 001 Av 5 010 Av 10 011 Av 20 100 110 Undefined 111 Av 1 Note that when the OPA0 is used the corresponding pin shared control bit should be properly configured to enable the AP pin function OPCM Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0...

Page 113: ...ter These two signals can also be output on PA6 and PA7 respectively by properly configuring the associated pin shared control bits A kind of A D converter interrupt i e Int_AHL_Lim can be used for phase current detection which will be introduced more in the A D Converter chapter Phase Current Detect Register There are two registers to control the on off function of the phase current detection cir...

Page 114: ...ver Transistor pairs being simultaneously on The Polarity circuit can select the output polarity of the BLDC motor output control port to support many different types of external MOS gate drive device circuit combinations The Motor Protect circuit includes many detection circuits for functions such as a motor stall condition over current condition etc The Hall Sensor Decoder circuit is a six step ...

Page 115: ... into the corresponding PWM registers 10 bit PWM p down co nter CKT PWMR fPWM PWM0 PWMP_Int PWMD0 _Int PWMC DUTR0 PRDR PWM Block Diagram PWMP Old PWMD_CH0 Old PWMD_CH0 New PWMP New PWMD_CH0 New PWMP New New PWM D ty New PWM Period PWMO PWM Edge Aligned mode Timing Diagram PWMP Old PWMD_CH0 Old PWMD_CH0 New PWMP New PWMD_CH0 New PWMP New New PWM D ty New PWM Period PWMO Center align mode 1 Center a...

Page 116: ...s of registers The DUTRnL DUTRnH register pair is used for PWM duty control for adjustment of the motor output power The PRDRL PRDRH register pair are used together to form a 10 bit value to setup the PWM period for PWM frequency adjustment Being able to change the PWM frequency is useful for motor characteristic matching for problems such as noise reduction and resonance The PWMRL PWMRH registers...

Page 117: ... interrupt only in count up condition 10 Center aligned mode duty interrupt only in count down condition 11 Center aligned mode duty interrupt in count up or down condition Bit 0 PWMLD PWM PRDR and DUTRn n 0 3 register update control 0 The register values of PRDR and DUTRn n 0 3 are never loaded to counter and comparator registers 1 The PRDR register value will be loaded to counter register after ...

Page 118: ...t 1 bit 0 10 bit DUTRn Register bit 9 bit 8 PRDRL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 10 bit PWM Period Low Byte Register bit 7 bit 0 10 bit PRDR Register bit 7 bit 0 PRDRH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 10 bit PWM Period High Byte R...

Page 119: ...101 3 Gate Driver MAT MAB MBT MBB MCT MCB PWMO Hall Sensor Decoder 12 6 HAT HAB HBT HBB HCT HCB Mask GAT GAB GBT GBB GCT GCB MCF PLC Dead Time Insert Staggered Circuit AT2 AB2 BT2 BB2 CT2 CB2 AT0 AB0 BT0 BB0 CT0 CB0 AT1 AB1 BT1 BB1 CT1 CB1 MCD PWMMD PWMME MCD PROTECTOC BRKE PROTECT Mask Function Block Diagram Motor U V W Power MOS Moto HV MAT MBT MCT MAB MBB MCB Mask Switching The internal mask ci...

Page 120: ...W POR 0 0 1 0 0 Bit 7 MSKMS Mask Mode selection 0 Hardware Mask Mode 1 Software Mask Mode Bit 6 4 Unimplemented read as 0 Bit 3 MPWMS Hardware Mask PWM Mode selection 0 Complementary output 1 Non complementary output This bit selection is invalid when in the Software Mask Mode where the PWM mode selection is determined by the PWMME register Bit 2 MPWE PWM output control 0 PWM output disable AT0 BT...

Page 121: ... 1 0 PWMO PWMB 1 1 0 0 1 1 0 0 PWMS 0 HCT HCB CT0 CB0 PWMS 1 HCT HCB CT0 CB0 0 0 0 0 0 0 0 0 0 1 PWMB PWMO 0 1 0 1 1 0 1 0 1 0 PWMO PWMB 1 1 0 0 1 1 0 0 Non complementary control MPWMS 1 PWMS 0 HAT HAB AT0 AB0 PWMS 1 HAT HAB AT0 AB0 0 0 0 0 0 0 0 0 0 1 0 PWMO 0 1 0 1 1 0 1 0 1 0 PWMO 0 1 1 0 0 1 1 0 0 PWMS 0 HBT HBB BT0 BB0 PWMS 1 HBT HBB BT0 BB0 0 0 0 0 0 0 0 0 0 1 0 PWMO 0 1 0 1 1 0 1 0 1 0 PWMO...

Page 122: ...PWMO Current Path 5 2 PWMO Current Path 1 2 PMEN PMD PMEN PMD PMEN PMD PMEN PMD 1 1 1 1 0 0 1 0 x x 0 0 1 0 0 0 x x 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 0 x x 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 x 1 1 1 0 1 1 1 0 0 x 0 0 0 x 1 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 1 0 0 x Software Mask Mode Circuit Note 1 If the mask mode is enabled when GxT and GxB x A B or C are masked simultaneously the two lines of each pa...

Page 123: ...d as 0 Bit 5 0 PMDn PWM mask data bit when PMEn 1 n 0 5 0 Output logic low 1 Output logic high Brake Mode The brake mode has the highest priority than other modes When this mode is activated the external gate driver transistor pair top arm will be off and the bottom arm will be on The brake truth decode table is shown below BRKE 1 AT0 BT0 CT0 AB0 BB0 CB0 0 0 0 1 1 1 Motor Protect Mode When the mot...

Page 124: ...Time is inserted When the AT0 AB0 BT0 BB0 CT0 CB0 outputs experience a falling edge then the outputs remain unchanged The Dead Time Insertion Circuit is only used during motor control The Dead Time function is controlled by the DTE bit in the DTS register AT0 AB0 BT0 BB0 CT0 CB0 Dead Time Insertion Dead Time Insertion Dead Time Insertion Dead Time Insertion 1 Rising Add Dead Time Insertion 2 Falli...

Page 125: ...atus A single register PLC is used for overall control PLC Register Bit 7 6 5 4 3 2 1 0 Name PCBC PCTC PBBC PBTC PABC PATC R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 PCBC C pair Bottom port gate output control 0 Non inverse output 1 Inverse output Bit 4 PCTC C pair Top port gate output control 0 Non inverse output 1 Inverse output Bit 3 PBBC B pair Bottom por...

Page 126: ...lected by setting the HDMS bit high If the HDMS bit is zero then SHA SHB SHC will be used instead of the actual Hall Sensor signals Hall Sensor Noise Filter This device includes a Hall Noise Filter function to filter out the effects of noise generated by the large switching currents of the motor driver This generated noise may affect the Hall Sensor inputs H1 H2 H3 which in turn may result in inco...

Page 127: ... SEL0 bits and set the selected TM to run in the Compare Match Output Mode Step 3 Use the HDLY_MSEL bit to select the Hall Delay circuit operating mode The default value of HDLY_MSEL is zero which will disable the Hall Delay circuit If the HDLY_MSEL bit is set high then the Hall Delay circuit will be enabled Step 4 Enable the Hall Decoder using the HDCEN bit The following points should be noted re...

Page 128: ... 2 0 D D PTM0 16 bit PTM PTM1 16 bit PTM PTM3 10 bit PTM Hall Noise Filter HDCD HA HB HC HDLY_MSEL HAT HAB HBT HBB HCT HCB CTM_SEL 1 0 SHA SHB SHC HDMS Hall Delay Circuit HDCEN HA0 HB0 HC0 HA1 HB1 HC1 HA2 HB2 HC2 SA SB SC FHA FHB FHC D Delay Function Block Diagram HA0 HB0 HC0 SA SB SC Delay Time Delay Function Timing ...

Page 129: ...HDCT2 5 0 0 1 1 0 1 1 HDCT3 5 0 0 0 1 0 0 1 HDCT4 5 0 0 0 0 1 0 1 HDCT5 5 0 Backword HDCEN 1 FRS 1 BRKE 0 60 Degree 120 Degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB 1 0 0 1 0 0 HDCT6 5 0 1 1 0 1 1 0 HDCT7 5 0 1 1 1 0 1 0 HDCT8 5 0 0 1 1 0 1 1 HDCT9 5 0 0 0 1 0 0 1 HDCT10 5 0 0 0 0 1 0 1 HDCT11 5 0 Brake BRKE 1 HDCEN X FRS X 60 Degree 120 Degree Bit5 Bit4 Bit3 Bit2...

Page 130: ... MBB MCB Power MOS MBT MBB MCT MCB MAT MAB HT66FM5440 IR2101 3 HBT HCT HBB HCB HAB Motor Drive Signal Timing Diagram Forward Direction S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 SA SB Sc Hall sensor 120 degree Motor Backward N S Ha Hb Hc 2 pole Motor Motor U V W Moto HV MAT MBT MCT MAB MBB MCB Power MOS MBT MBB MCT MCB MAT MAB HT66FM5440 IR2101 3 HAT HBT HCT HBB HCB HAB Motor Drive Signal Timing Diagram ...

Page 131: ... control for INTC 00 Disable 01 Rising edge trigger 10 Falling edge trigger 11 Dual edge trigger Bit 3 2 INTBS1 INTBS0 FHB Interrupt edge control for INTB 00 Disable 01 Rising edge trigger 10 Falling edge trigger 11 Dual edge trigger Bit 1 0 INTAS1 INTAS0 FHA Interrupt edge control for INTA 00 Disable 01 Rising edge trigger 10 Falling edge trigger 11 Dual edge trigger HDCR Register Bit 7 6 5 4 3 2...

Page 132: ...t 2 SHC Software Hall C Bit 1 SHB Software Hall B Bit 0 SHA Software Hall A HDCTn Register n 0 11 Bit 7 6 5 4 3 2 1 0 Name HATDn HABDn HBTDn HBBDn HCTDn HCBDn R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 HATDn AT output state control 0 Output 0 1 Output 1 Bit 4 HABDn AB output state control 0 Output 0 1 Output 1 Bit 3 HBTDn BT output state control 0 Output 0 1 ...

Page 133: ...election fSYS fH 000 fSYS 2 001 fSYS 4 010 fSYS 8 011 fSYS 16 100 fSYS 32 101 fSYS 64 110 fSYS 128 111 Unuse Motor Protection Function Motors normally require large currents for their operation and as such need to be protected from the problems of excessive drive currents and motor stalling etc to reduce motor damage or for safety reasons This device includes a range of protection and safety featu...

Page 134: ...the Brake Mode where the top arm is off and the bottom arm is on and the second is the Free Running Mode where both top and bottom arms are off The FMOS bit in the MCF register determines which type is used The motor protection circuit can operate in two modes which is selected by the MPTC2 register One mode is the Fault Mode and the other is Pause Mode In the Fault Mode activating the protect fun...

Page 135: ...gnored and the over current protection logics in the OCPS register are used to immediately switch off drive signals to protect the power MOS To remove the PROTECTOC over current protection mechanism set the OCPSE bit from low to high to trigger the software reset function thus pulling the PROTECTOC signal to low after which the normal polarity drive signals will be recovered For the MOS current li...

Page 136: ...s with Hall Sensors the 16 bit CAPTM can be used to monitor the H1 H2 and H3 inputs for rotor speed detection The software will setup the CAPTMAH and CAPTMAL registers to monitor the Hall sensor input pins H1 H2 and H3 for rotor speed control If an abnormal situation exists a CapTM_Cmp or CapTM_Over interrupt will be generated which is described in the CAPTM section Stall Detrect Mechanism CapTM_C...

Page 137: ... Enable When the motor protection software mode has been enabled and triggered is should be removed by setting this bit from high to low and then high again Bit 5 CapOHE CapTM_Over Hardware Mode control 0 Disable 1 Enable Bit 4 CapCHE CapTM_Cmp Hardware Mode control 0 Disable 1 Enable Bit 3 ISHE Int_Is Hardware Mode control 0 Disable 1 Enable Bit 2 AHLHE Int_AHL_Lim Hardware Mode control 0 Disable...

Page 138: ...eset 1 Protection circuit allows restart of PWM output on the next PWM period when the Int_AHL_Lim interrupt has been reset Bit 2 ISPS Int_Is Pause Fault Mode selection 0 Fault Mode 1 Pause Mode In the Pause Mode to remove the Int_Is over current condition users must setup in the order of PSWE 1 PSWPS 1 PSWE 0 Bit 1 CAPCPS CapTM_Cmp Pause Mode selection 0 Undefined 1 Pause Mode Note that this bit ...

Page 139: ...CB C pair Bottom port gate output selection 0 Output 0 1 Output 1 Bit 4 OCPCT C pair Top port gate output selection 0 Output 0 1 Output 1 Bit 3 OCPBB B pair Bottom port gate output selection 0 Output 0 1 Output 1 Bit 2 OCPBT B pair Top port gate output selection 0 Output 0 1 Output 1 Bit 1 OCPAB A pair Bottom port gate output selection 0 Output 0 1 Output 1 Bit 0 OCPAT A pair Top port gate output ...

Page 140: ...these outputs Note that no chip select line exists as each device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C bus When two devices communicate with each other on the bidirectional I2 C bus one is known as the master device and one as the slave device Both master and slave can transmit and receive data however it is the master device that has...

Page 141: ...ck frequency and the configured debounce time to match the criterion shown in the following table I2 C Debounce Time Selection I2 C Standard Mode 100kHz I2 C Fast Mode 400kHz No Debounce fSYS 2 MHz fSYS 5 MHz 2 system clock debounce fSYS 4 MHz fSYS 10 MHz 4 system clock debounce fSYS 8 MHz fSYS 20 MHz I2 C Minimum fSYS Frequency I2 C Registers There are four control registers associated with the I...

Page 142: ...re two control registers for the I2 C interface IICC0 and IICC1 The register IICC0 is used for I2 C communication settings The IICC1 register contains the relevant flags which are used to indicate the I2 C communication status IICC0 Register Bit 7 6 5 4 3 2 1 0 Name IICDEB1 IICDEB0 IICEN R W R W R W R W POR 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 IICDEB1 IICDEB0 I2 C Debounce Time Selection ...

Page 143: ... this bit will be high if there is no match then the flag will be low Bit 5 HBB I2 C Bus busy flag 0 I2 C Bus is not busy 1 I2 C Bus is busy The HBB flag is the I2 C busy flag This flag will be 1 when the I2 C bus is busy which will occur when a START signal is detected The flag will be set to 0 when the bus is free which will occur when a STOP signal is detected Bit 4 HTX Select I2 C slave device...

Page 144: ...When a START signal is placed on the I2 C bus all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus The first seven bits of the data will be the slave address with the first bit being the MSB If the address of the slave device matches that of the transmitted address the HAAS bit in the IICC1 register will be set and an I2 C interrupt will be gen...

Page 145: ...rupt signal will be generated The next bit following the address which is the 8th bit defines the read write status and will be saved to the SRW bit of the IICC1 register The slave device will then transmit an acknowledge bit which is a low level as the 9th bit The slave device will also set the status flag HAAS when the addresses match As an I2 C bus interrupt can come from three sources when the...

Page 146: ...evel 0 before it can receive the next data byte If the slave transmitter does not receive an acknowledge bit signal from the master receiver then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2 C Bus The corresponding data will be stored in the IICD register If setup as a transmitter the slave device must first write the data to be transm...

Page 147: ... ISR Flow Chart I2 C Time out Control In order to reduce the problem of I2 C lockup due to reception of erroneous clock sources a time out function is provided If the clock source to the I2 C is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts counting on an I2 C bus START address match condition and is cleared...

Page 148: ... be reset and the registers will be reset into the following condition Registers After I2 C Time out IICD IICA IICC0 No change IICC1 Reset to POR condition The IICTOF flag can be cleared by the application program There are 64 time out periods which can be selected using bits in the IICTOC register The time out time is given by the formula 1 64 32 fSUB This gives a range of about 1ms to 64ms IICTO...

Page 149: ...es The integrated UART function contains the following features Full duplex asynchronous communication 8 or 9 bits character length Even odd or no parity options One or two stop bits Baud rate generator with 8 bit prescaler Parity framing noise and overrun error detection Support for interrupt on address detect last character bit 1 Separately enabled transmitter and receiver 2 byte Deep FIFO Recei...

Page 150: ... register is mapped onto the MCU Data Memory the Transmit Shift Register is not mapped and is therefore inaccessible to the application program Data to be received by the UART is accepted on the external RX pin from where it is shifted in LSB first to the Receiver Shift Register at a rate controlled by the Baud Rate Generator When the shift register is full the data will then be transferred from t...

Page 151: ... by an access to the TXR_RXR data register Bit 5 FERR Framing error flag 0 No framing error is detected 1 Framing error is detected The FERR flag is the framing error flag When this read only flag is 0 it indicates that there is no framing error When the flag is 1 it indicates that a framing error has been detected for the current character The flag can also be cleared by a software sequence which...

Page 152: ...ster The flag is not generated when a data character or a break is queued and ready to be sent Bit 0 TXIF Transmit TXR_RXR data register status 0 Character is not transferred to the transmit shift register 1 Character has transferred to the transmit shift register TXR_RXR data register is empty The TXIF flag is the transmit data register empty flag When this read only flag is 0 it indicates that t...

Page 153: ...most significant bit position with a parity bit Bit 4 PRT Parity type selection bit 0 Even parity for parity generator 1 Odd parity for parity generator This bit is the parity type selection bit When this bit is equal to 1 odd parity type will be selected If the bit is equal to 0 then even parity type will be selected Bit 3 STOPS Number of Stop bits selection 0 One stop bit format is used 1 Two st...

Page 154: ...e disabled with any pending data receptions being aborted In addition the receive buffers will be reset In this situation the RX pin will be set in a floating state If the RXEN bit is equal to 1 and the UARTEN bit is also equal to 1 the receiver will be enabled and the RX pin will be controlled by the UART Clearing the RXEN bit during a reception will cause the data reception to be aborted and wil...

Page 155: ...RXIF flags Bit 1 TIIE Transmitter Idle interrupt enable control 0 Transmitter idle interrupt is disabled 1 Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt If this bit is equal to 1 and when the transmitter idle flag TIDLE is set due to a transmitter idle condition the UART interrupt request flag will be set If this bit is equal to 0 the UART interr...

Page 156: ...lue can be calculated Calculating the Baud Rate and Error Values For a clock frequency of 4MHz and with BRGH cleared to zero determine the BRG register value N the actual baud rate and the error value for a desired baud rate of 4800 From the above table the desired baud rate BR fH 64 N 1 Re arranging this equation gives N fH BR 64 1 Giving a value for N 4000000 4800 64 1 12 0208 To obtain the clos...

Page 157: ...ed it will restart again in the same configuration Data Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length parity on off parity type address bits and the number of stop bits These factors are determined by the setup of various bits within the UCR1 register The BNO bit controls the number of data bits which can be set to eit...

Page 158: ... TX pin from the shift register with the least significant bit first In the transmit mode the TXR_RXR register forms a buffer between the internal bus and the transmitter shift register It should be noted that if 9 bit data format has been selected then the MSB will be taken from the TX8 bit in the UCR1 register The steps to initiate a data transfer can be summarized as follows Make the correct se...

Page 159: ... majority detect circuit to determine the logic level that has been placed onto the RX pin It should be noted that the RSR register unlike many other registers is not directly mapped into the Data Memory area and as such is not available to the application program for direct read write operations Receiving Data When the UART receiver is receiving data the data is serially shifted in on the externa...

Page 160: ...LE or RXIF flags will possibly be set Idle Status When the receiver is reading data which means it will be in between the detection of a start bit and the reading of a stop bit the receiver status flag in the USR register otherwise known as the RIDLE flag will have a zero value In between the reception of a stop bit and the detection of the next start bit the RIDLE flag will have a high value whic...

Page 161: ...ter idle receiver data available receiver overrun address detect and an RX pin wake up When any of these conditions are created if the global interrupt enable bit interrupt priority enable bit and its corresponding interrupt control bit are enabled and the stack is not full the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program Fou...

Page 162: ...e last bit of the received word is set If the ADDEN bit is not enabled then a Receiver Data Available interrupt will be generated each time the RXIF flag is set irrespective of the data last bit status The address detect mode and parity enable are mutually exclusive functions Therefore if the address detect mode is enabled then to ensure correct operation the parity function should be disabled by ...

Page 163: ... to monitor the power supply voltage VDD and provide a warning signal should it fall below a certain level This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages as it allows an early warning battery low signal to be generated The Low Voltage Detector also has the capability of generating an interrupt signal LVD Register Th...

Page 164: ...LEEP mode the low voltage detector will be disabled even if the LVDEN bit is high After enabling the Low Voltage Detector a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions VDD LVDEN LVDO VLVD tLVDS LVD Operation...

Page 165: ...angle The MDUs in replacing the software multiplication and division operations can therefore save large amounts of computing time as well as the Program and Data Memory space They also reduce the overall microcontroller loading and results in the overall system performance improvements fSYS MDU0R0 MDU0R1 8 bit Dividend 8 bit Multiplicand 8 bit Divisor 8 bit Multiplier Shift Control MD0DONE MD0OV ...

Page 166: ... MDU1R0 D7 D6 D5 D4 D3 D2 D1 D0 MDU1R1 D7 D6 D5 D4 D3 D2 D1 D0 MDU1R2 D7 D6 D5 D4 D3 D2 D1 D0 MDU1R3 D7 D6 D5 D4 D3 D2 D1 D0 MDU1R4 D7 D6 D5 D4 D3 D2 D1 D0 MDU1R5 D7 D6 D5 D4 D3 D2 D1 D0 MDU1CTRL MD1EF MD1OV 16 Bit MDU1 Registers List MDU0Rn Register n 0 1 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D7 D0 8 bit MDU0 dat...

Page 167: ...is determined by the MD0S bit in the MDU0CTRL register Before a multiplication or division operation starts write the multiplicand dividend into the MDU0R0 register and the multiplier divisor into the MDU0R1 register After the multiplication or division operation is completed the MDU0R0 register stores the multiplication product low byte or the division quotient the MDU0R1 register stores the mult...

Page 168: ...ing operation The calculation time necessary for these MDU1 operations are different During the calculation time any read write access to the six MDU1 data registers is forbidden After the completion of each operation it is necessary to check the operation status in the MDU1CTRL register to make sure that whether the operation is correct or not Then the operation result can be read out from the co...

Page 169: ... needs The device contains several external interrupt and internal interrupt functions The external interrupts are generated by the action of the external H1 H2 H3 NFIN and INT1 pins while the internal interrupts are generated by various internal functions including the TMs Comparator 0 16 bit CAPTM Time Base UART I2 C LVD and the A D converter Interrupt Registers Overall interrupt control which b...

Page 170: ...10 bit PTM3 TM3PE TM3PF 14 TM3AE TM3AF Multi function 7 I2 C UART LVD Time Base IICE IICF 15 UARTE UARTF LVE LVF TBE TBF Interrupt Name Interrupt Register Bit Name Interrupt Number Register Name Bit 7 6 5 4 3 2 1 0 INTEG0 HSEL INTCS1 INTCS0 INTBS1 INTBS0 INTAS1 INTAS0 INTEG1 INTPRI1 INTPRI0 INT1S1 INT1S0 INTC0 Int_pri3F Int_pri2F Int_pri1F Int_pri3E Int_pri2E Int_pri1E EMI INTC1 Int_pri7F Int_pri6...

Page 171: ...ge control for INTA 00 Disable 01 Rising edge trigger 10 Falling edge trigger 11 Dual edge trigger INTEG1 Register Bit 7 6 5 4 3 2 1 0 Name INTPRI1 INTPRI0 INT1S1 INT1S0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 INTPRI1 INTPRI0 Interrupt Vector 04H and 08H priority preempt control Described elsewhere Bit 1 0 INT1S1 INT1S0 Interrupt edge control for INT1 pin 00 Disable...

Page 172: ...nt_pri7E Int_pri6E Int_pri5E Int_pri4E R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 Int_pri7F Interrupt priority 7 request flag 0 No request 1 Interrupt request Bit 6 Int_pri6F Interrupt priority 6 request flag 0 No request 1 Interrupt request Bit 5 Int_pri5F Interrupt priority 5 request flag 0 No request 1 Interrupt request Bit 4 Int_pri4F Interrupt priority 4 request flag 0 No r...

Page 173: ...l 0 No request 1 Interrupt request Bit 2 Int_pri10E Interrupt priority 10 control 0 Disable 1 Enable Bit 1 Int_pri9E Interrupt priority 9 control 0 Disable 1 Enable Bit 0 Int_pri8E Interrupt priority 8 control 0 Disable 1 Enable INTC3 Register Bit 7 6 5 4 3 2 1 0 Name Int_pri15F Int_pri14F Int_pri13F Int_pri12F Int_pri15E Int_pri14E Int_pri13E Int_pri12E R W R W R W R W R W R W R W R W R W POR 0 0...

Page 174: ... 4 HALAF Hall sensor A interrupt request flag 0 No request 1 Interrupt request Bit 3 Unimplemented read as 0 Bit 2 HALCE Hall sensor C interrupt control 0 Disable 1 Enable Bit 1 HALBE Hall sensor B interrupt control 0 Disable 1 Enable Bit 0 HALAE Hall sensor A interrupt control 0 Disable 1 Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name PWMPF PWMD2F PWMD1F PWMD0F PWMPE PWMD2E PWMD1E PWMD0E R W R W R...

Page 175: ...request Bit 4 ISAEOCF A D auto scan interrupt request flag 0 No request 1 Interrupt request Bit 3 2 Unimplemented read as 0 Bit 1 AEOCE A D normal conversion interrupt control 0 Disable 1 Enable Bit 0 ISAEOCE A D auto scan interrupt control 0 Disable 1 Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name TM2AF TM2PF TM2AE TM2PE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 TM2AF P...

Page 176: ...E PTM0 Comparator A match interrupt control 0 Disable 1 Enable Bit 0 TM0PE PTM0 Comparator P match interrupt control 0 Disable 1 Enable MFI5 Register Bit 7 6 5 4 3 2 1 0 Name TM1AF TM1PF TM1AE TM1PE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 TM1AF PTM1 Comparator A match interrupt request flag 0 No request 1 Interrupt request Bit 4 TM1PF PTM1 Comparator P match interrupt...

Page 177: ...PTM3 Comparator P match interrupt control 0 Disable 1 Enable MFI7 Register Bit 7 6 5 4 3 2 1 0 Name TBF LVF UARTF IICF TBE LVE UARTE IICE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TBF Time Base interrupt request flag 0 No request 1 Interrupt request Bit 6 LVF LVD interrupt request flag 0 No request 1 Interrupt request Bit 5 UARTF UART interrupt request flag 0 No request 1 Inter...

Page 178: ...priority flags must be cleared once Vector Interrupt Priority Enable Bit Request Flag Note 04H Interrupt priority 1 Int_pri1E Int_pri1F Highest Priority 08H Interrupt priority 2 Int_pri2E Int_pri2F 0CH Interrupt priority 3 Int_pri3E Int_pri3F 10H Interrupt priority 4 Int_pri4E Int_pri4F 14H Interrupt priority 5 Int_pri5E Int_pri5F 18H Interrupt priority 6 Int_pri6E Int_pri6F 1CH Interrupt priority...

Page 179: ...ired interrupt number in interrupt priority 6 Bit 3 0 IP5R3 IP5R0 Setup the required interrupt number in interrupt priority 5 Pri_name3 Register Bit 7 6 5 4 3 2 1 0 Name IP8R3 IP8R2 IP8R1 IP8R0 IP7R3 IP7R2 IP7R1 IP7R0 R W R W R W R W R W R W R W R W R W POR 1 0 0 0 0 1 1 1 Bit 7 4 IP8R3 IP8R0 Setup the required interrupt number in interrupt priority 8 Bit 3 0 IP7R3 IP7R0 Setup the required interru...

Page 180: ...wever the interrupt vector 08H can not suspend the vector 04H subroutine even when the 04H vector preempt function is disabled It should be noted that when a preempt interrupt occurs and the stack is full the requested preempt interrupt will not be immediately serviced until the stack is not full After the current higher priority interrupt has been serviced the program will return to the last susp...

Page 181: ...and the program will not jump to the relevant interrupt vector The global interrupt enable bit if cleared to zero will disable all interrupts When an interrupt is generated the Program Counter which stores the address of the next instruction to be executed will be transferred onto the stack The Program Counter will then be loaded with a new address which will be the value of the corresponding inte...

Page 182: ...is in SLEEP or IDLE Mode Int_pri1F Int_pri1 F Int_pri1 E 04H 0 H Int_pri F 0CH Req est Flags Enable Bits Master Enable Vector EMI a to disabled in ISR Low High 4H 3 H Int_pri14F Int_pri14E Int_pri9F Int_pri9E 1CH 0H Int_pri F Int_pri E 10H Int_pri13F Int_pri13E 14H Int_pri3F Int_pri3E Int_pri F Int_pri E Int_pri6F Int_pri6E Int_pri5F Int_pri5E 1 H EMI EMI EMI EMI EMI EMI EMI EMI 3CH H Int_pri10F I...

Page 183: ...WMD0E PWMD1 PWMD1F PWMD1E PWMD2 PWMD2F PWMD2E Noise filter 13 Multi Function 1 3 AHL_Lim 7 6 CapTM_Over 5 CapTM_Cmp LVD LVDF LVDE PTM2 A TM2AF TM2AE PTM2 P TM2PF TM2PE PTM0 A TM0AF TM0AE PTM0 P TM0PF TM0PE PTM3 A TM3AF TM3AE PTM3 P TM3PF TM3PE Multi Function 0 10 Multi Function 4 PTM1 A TM1AF TM1AE PTM1 P TM1PF TM1PE 11 Multi Function 5 I2 C IICF IICE UART UARTF UARTE PWMD3 4 AEOCF AEOCE ADC EOC I...

Page 184: ... Hall sensor interrupt A choice of either rising or falling or both edge types can be chosen to trigger a Hall sensor interrupt Note that the INTEG0 register can also be used to disable the Hall sensor interrupt functions External Interrupt 1 The external interrupt 1 has its own independent interrupt number and is controlled by signal transitions on the INT1 pin After being configured with a desir...

Page 185: ...ilter interrupt Note that the NF_VIL register can also be used to disable the noise filter interrupt function Comparator Interrupt The comparator interrupt has its own independent interrupt number and is controlled by the internal comparator 0 After being configured with a desired interrupt priority level a comparator interrupt request will take place when the relevant interrupt priority request f...

Page 186: ...M Period match interrupt known as PWMP and four PWM Duty match interrupts known as PWMDn n 0 3 The PWMP and PWMD0 PWMD2 interrupts are contained in multi function interrupt 1 and they share the same interrupt number The PWMD3 interrupt has its independent number Regarding the PWMP and PWMD0 PWMD2 interrupts after being configured with the desired interrupt priority level a PWM interrupt request wi...

Page 187: ... to the respective interrupt vector address the global interrupt enable bit EMI the A D normal conversion interrupt enable bit AEOCE or the A D auto scan interrupt enable bit ISAEOCE and associated interrupt priority enable bit must first be set When the interrupt is enabled the stack is not full and the A D normal conversion process or auto scan process has ended a subroutine call to the interrup...

Page 188: ...d the associated interrupt priority request flag are set which occurs when a byte of data has been received or transmitted by the I2 C interface I2 C address match or I2 C time out occurs To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and the I2 C Interface Interrupt enable bit IICE and the realted interrupt priority enable bit must fi...

Page 189: ...ing the same interrupt number with other interrupt sources in the same group After being configured with the desired interrupt priority level an LVD Interrupt request will take place when the LVD Interrupt request flag LVF and the associated interrupt priority request flag are set which occurs when the Low Voltage Detector function detects a low power supply voltage To allow the program to branch ...

Page 190: ...cally cleared the individual request flag of the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If only one stack is left and the interrupt is not well controlled the original control sequence will be d...

Page 191: ...66FM5440 device and are coordinated by the BLDC motor control circuit These functions include a 10 bit motor dedicated PWM mask function Hall sensor decoder and motor protection function which combined with the OCP capture timer etc provide the advantage of fast system protection From the perspective of a control system the main points of each function will be explained in the following Hall Senso...

Page 192: ... solution to introduce the BLDC motor control system OCP Hall Sensor Decoder HT8 1T 12 bit ADC BLDC Motor Detect VDC bus current Detect VDC bus voltage BLDC Motor Control Circuit VDC bus LDO HT66FM5440 P N MOSFET 3 Pairs Speed Command DC Power Pre Driver Hall A Hall Sensor 3 Hall B Hall C Hall Noise Filter R_Shunt BLDC Motor Control with Hall Sensor 1 The DC power is a low voltage system which pro...

Page 193: ...d phase change logic according to the Hall sensor signals and protection signals to implement motor operating control Hardware Circuit DC Bus 5V GND Vin 1 GND 2 Vout 3 78L05 1 2 DC Power U S1N 1 G1N 2 S2N 3 G2N 4 D1N 5 D1N 6 D2N 7 D2N 8 P N MOSFET AT GND DC Bus DC Bus GND AB DC Bus S1N 1 G1N 2 S2N 3 G2N 4 D1N 5 D1N 6 D2N 7 D2N 8 P N MOSFET GND DC Bus DC Bus GND DC Bus BB BT V R_Shunt GND S1N 1 G1N...

Page 194: ...re cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only o...

Page 195: ...h instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual Bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of ...

Page 196: ...h Carry result in Data Memory 1Note Z C AC OV SC CZ DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memor...

Page 197: ...x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None ITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL m Increment table pointer TBLP first and Read t...

Page 198: ...sult in Data Memory 2Note C Logic Operation LAND A m Logical AND Data Memory to ACC 2 Z LOR A m Logical OR Data Memory to ACC 2 Z LXOR A m Logical XOR Data Memory to ACC 2 Z LANDM A m Logical AND ACC to Data Memory 2Note Z LORM A m Logical OR ACC to Data Memory 2Note Z LXORM A m Logical XOR ACC to Data Memory 2Note Z LCPL m Complement Data Memory 2Note Z LCPLA m Complement Data Memory with result ...

Page 199: ...result in ACC 2Note None Table Read LTABRD m Read table to TBLH and Data Memory 3Note None LTABRDL m Read table last page to TBLH and Data Memory 3Note None LITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL m Increment table pointer TBLP first and Read table last page to TBLH and Data Memory 3Note None Miscellaneous LCLR m Clear Data Memory 2No...

Page 200: ...ator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C SC ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC AND A m Logical AND Data Memory to ACC Description...

Page 201: ...reviously contained a 1 are changed to 0 and vice versa Operation m m Affected flag s Z CPLA m Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented 1 s complement Bits which previously contained a 1 are changed to 0 and vice versa The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchange...

Page 202: ...ation m m 1 Affected flag s Z INCA m Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1 The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC m 1 Affected flag s Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address Program execu...

Page 203: ...ag s Z RET Return from subroutine Description The Program Counter is restored from the stack Program execution continues at the restored address Operation Program Counter Stack Affected flag s None RET A x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data Program execution co...

Page 204: ...7 replaces the Carry bit and the original carry flag is rotated into the bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 C C m 7 Affected flag s C RR m Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7 Operation m i m i 1...

Page 205: ...CC m C Affected flag s OV Z AC C SC CZ SBCM A m Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Data Memory Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive...

Page 206: ...on while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m 1 Skip if ACC 0 Affected flag s None SNZ m i Skip if Data Memory is not 0 Description If the specified Data Memory is not 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruct...

Page 207: ...ory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetche...

Page 208: ...TBLH Operation m program code low byte TBLH program code high byte Affected flag s None ITABRDL m Increment table pointer low byte first and read table last page to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH ...

Page 209: ...red in the Accumulator Operation ACC ACC m Affected flag s OV Z AC C SC LADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC LAND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform ...

Page 210: ...the high nibble is greater than 9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Op...

Page 211: ... are rotated left by 1 bit with bit 7 rotated into bit 0 Operation m i 1 m i i 0 6 m 0 m 7 Affected flag s None LRLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6...

Page 212: ...emory and the carry flag are rotated right by 1 bit Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 C C m 0 Affected flag s C LSBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and ...

Page 213: ...i of the specified Data Memory is set to 1 Operation m i 1 Affected flag s None LSIZ m Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is no...

Page 214: ...set to 1 Operation m ACC m Affected flag s OV Z AC C SC CZ LSWAP m Swap nibbles of Data Memory Description The low order and high order nibbles of the specified Data Memory are interchanged Operation m 3 m 0 m 7 m 4 Affected flag s None LSWAPA m Swap nibbles of Data Memory with result in ACC Description The low order and high order nibbles of the specified Data Memory are interchanged The result i...

Page 215: ...ted flag s None LITABRD m Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the program code addressed by the table pointer TBHP and TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None LITABRDL m Incre...

Page 216: ...intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Material...

Page 217: ...nsions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 0098 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 9 9 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 218: ...olely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserves th...

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