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HT66FM5440
Brushless DC Motor A/D Flash MCU
HT66FM5440
Brushless DC Motor A/D Flash MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
their internal system architecture. The range of the device take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching, instruction execution
and data write-back operation are overlapped, hence instructions are effectively executed in one
or two cycles for most of the standard or extended instructions respectively, with the exception of
branch or call instructions which needs one more cycle. An 8-bit wide ALU is used in practically
all instruction set operations, which carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data
through the Accumulator and the ALU. Certain internal registers are implemented in the Data
Memory and can be directly or indirectly addressed. The simple addressing methods of these
registers along with additional architectural features ensure that a minimum of external components
is required to provide a functional I/O and A/D control system with maximum reliability and
flexibility. This makes the device suitable for low-cost, high-volume production for controller
applications.
Clocking and Pipelining
The main system clock, derived from the HIRC oscillator is also used as the instruction clock. The
Program Counter is incremented at the beginning of the the system clock during which time a new
instruction is fetched. The following two system clocks carry out the instruction decoding/execution
and the data write-back functions respectively. Although the instruction fetching, decoding/
execution and data write-back operations take place in consecutive instruction cycles, the pipelining
structure of the microcontroller ensures that instructions are effectively executed in one instruction
cycle. The exception to this are instructions where the contents of the Program Counter are changed,
such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle
to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
Fetch Inst. (PC)
(System Clock)
f
SYS
Program Co�nter
PC
PC+1
PC+�
Pipelining
Exec�te Inst. (PC-1)
Fetch Inst. (PC+1)
Exec�te Inst. (PC)
Fetch Inst. (PC+�)
Exec�te Inst. (PC+1)
PC+3
Data Write (PC-�)
Data Write (PC-1)
Data Write (PC)
Fetch Inst. (PC+3)
Exec�te Inst. (PC+�)
Data Write (PC+1)
Fetch
Exec�te
Write
System Clocking and Pipelining
