2.2.26 (3) DIVXS
DIVXS (DIVide eXtend as Signed)
Divide Signed
DIVXS instruction, Division by Zero, and Overflow
Since the DIVXS instruction does not detect division by zero or overflow, applications should
detect and handle division by zero and overflow using techniques similar to those used in the
following program.
1. Programming solution for DIVXS.B R0L, R1
Example 1: Convert dividend and divisor to non-negative numbers, then use DIVXU
programming solution for zero divide and overflow
MOV.B
R0L, R0L
; Test divisor
BEQ
ZERODIV
; Branch to ZERODIV if R0L = 0
ANDC
#AF, CCR
; Clear CCR user bits (bits 6 and 4) to 0
BPL
L1
; Branch to L1 if N flag = 0 (positive divisor)
NEG.B
R0L
; Take 2’s complement of R0L to make sign positive
ORC
#10, CCR
; Set CCR bit 4 to 1
L1:
MOV.W
R1.R1
; Test dividend
BPL
L2
; Branch to L2 if N flag = 0 (positive dividend)
NEG.W
R1
; Take 2’s complement of R1 to make sign positive
XORC
#50, CCR
; Invert CCR bits 6 and 4
L2:
MOV.B
R1H, R2L
;
EXTU.W
R2
;
DIVXU.B
R0L, R2
;
Use DIVXU.B instruction to divide non-negative dividend
MOV.B
R2H, R1H
;
by positive divisor
DIVXU.B
R0L, R1
;
16 bits ÷ 8 bits
→
quotient (16 bits) and remainder (8 bits)
MOV.B
R2L, R2H
;
(See DIVXU Instruction, Zero Divide, and Overflow)
MOV.B
R1L, R2L
;
STC
CCR, R1L
; Copy CCR contents to R1L
BTST
#6, R1L
; Test CCR bit 6
BEQ
L3
; Branch to L3 if bit 6 = 1
NEG.B
R1H
; Take 2’s complement of R1H to make sign of remainder negative
L3:
BTST
#4, R1L
; Test CCR bit 4
BEQ
L4
; Branch to L4 if bit 4 = 1
NEG.W
R2
; Take 2’s complement of R2 to make sign of quotient negative
L4:
RTS
ZERODIV:
; Zero-divide handling routine
This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H.
R1
R1H
R2
R0L
Divisor
Dividend
Remainder
Quotient
86
