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Hitachi H8/300H Series, Programming Manual

The Hitachi H8/300H Series Programming Manual is an essential resource for users seeking detailed instructions on programming these powerful processors. Easily downloadable for free from manualshive.com, this comprehensive manual provides in-depth information to help you maximize the potential of your H8/300H Series product.

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2.2.50 (2) ROTXR (W) .................................................................................................. 157
2.2.50 (3) ROTXR (L) ................................................................................................... 158
2.2.51

RTE................................................................................................................ 159

2.2.52

RTS ................................................................................................................ 160

2.2.53 (1) SHAL (B) ...................................................................................................... 161
2.2.53 (2) SHAL (W) ..................................................................................................... 162
2.2.53 (3) SHAL (L)....................................................................................................... 163
2.2.54 (1) SHAR (B) ...................................................................................................... 164
2.2.54 (2) SHAR (W) ..................................................................................................... 165
2.2.54 (3) SHAR (L) ...................................................................................................... 166
2.2.55 (1) SHLL (B)....................................................................................................... 167
2.2.55 (2) SHLL (W)...................................................................................................... 168
2.2.55 (3) SHLL (L) ....................................................................................................... 169
2.2.56 (1) SHLR (B)....................................................................................................... 170
2.2.56 (2) SHLR (W) ..................................................................................................... 171
2.2.56 (3) SHLR (L)....................................................................................................... 172
2.2.57

SLEEP ........................................................................................................... 173

2.2.58 (1) STC (B) ......................................................................................................... 174
2.2.58 (2) STC (W) ........................................................................................................ 175
2.2.59 (1) SUB (B) ......................................................................................................... 177
2.2.59 (2) SUB (W) ........................................................................................................ 178
2.2.59 (3) SUB (L) ......................................................................................................... 179
2.2.60

SUBS ............................................................................................................. 180

2.2.61

SUBX ............................................................................................................ 181

2.2.62

TRAPA .......................................................................................................... 182

2.2.63 (1) XOR (B) ........................................................................................................ 183
2.2.63 (2) XOR (W) ....................................................................................................... 184
2.2.63 (3) XOR (L)......................................................................................................... 185
2.2.64

XORC ............................................................................................................ 186

2.3

Instruction Set Summary ................................................................................................ 187

2.4

Instruction Codes ............................................................................................................ 200

2.5

Operation Code Map....................................................................................................... 209

2.6

Number of States Required for Instruction Execution ................................................... 212

2.7

Condition Code Modification ......................................................................................... 221

2.8

Bus cycles During Instruction Execution ....................................................................... 226

Section 3

Processing States

........................................................................................... 239

3.1

Overview......................................................................................................................... 239

3.2

Program Execution State ................................................................................................ 241

3.3

Exception-Handling State ............................................................................................... 241
3.3.1

Types of Exception Handling and Their Priority................................................ 241

Summary of Contents for H8/300H Series

Page 1: ...H8 300H Series Programming Manual HITACHI ADE 602 053A ...

Page 2: ...umber of Mnemonic amended States Required for Execution P114 2 2 35 4 MOV B Description Description amended P117 2 2 35 5 MOV W Operand Format and Number of Table contents amended States Required for Execution P119 2 2 35 6 MOV L Operand Format and Number of Table contents amended States Required for Execution P123 2 2 35 8 MOV W Operand Format and Number of Table contents amended States Required ...

Page 3: ...f execution states amended 1 Data Transfer Instructions PUSH L ERn Number of execution states amended P191 2 Arithmetic Operation Instructions DAA Rd Condition code amended P192 2 Arithmetic Operation Instructions CMP L xx 32 ERd Number of execution states amended P196 5 Bit Manipulation Instructions Table amended P197 6 Branch Instructions Added P198 P198 7 System Control Instructions LDC ERs CCR...

Page 4: ...tructions and Addressing Modes 16 1 6 3 Tables of Instructions Classified by Function 18 1 6 4 Basic Instruction Formats 27 1 6 5 Addressing Modes and Effective Address Calculation 28 Section 2 Instruction Descriptions 35 2 1 Tables and Symbols 35 2 1 1 Assembler Format 36 2 1 2 Operation 37 2 1 3 Condition Code 38 2 1 4 Instruction Format 38 2 1 5 Register Specification 39 2 1 6 Bit Data Access i...

Page 5: ... B 72 2 2 22 2 CMP W 73 2 2 22 3 CMP L 74 2 2 23 DAA 75 2 2 24 DAS 77 2 2 25 1 DEC B 79 2 2 25 2 DEC W 80 2 2 25 3 DEC L 81 2 2 26 1 DIVXS B 82 2 2 26 2 DIVXS W 84 2 2 26 3 DIVXS 86 2 2 27 1 DIVXU B 90 2 2 27 2 DIVXU W 91 2 2 28 1 EEPMOV B 95 2 2 28 2 EEPMOV W 96 2 2 29 1 EXTS W 98 2 2 29 2 EXTS L 99 2 2 30 1 EXTU W 100 2 2 30 2 EXTU L 101 2 2 31 1 INC B 102 2 2 31 2 INC W 103 2 2 31 3 INC L 104 2...

Page 6: ...9 2 MULXU W 131 2 2 40 1 NEG B 132 2 2 40 2 NEG W 133 2 2 40 3 NEG L 134 2 2 41 NOP 135 2 2 42 1 NOT B 136 2 2 42 2 NOT W 137 2 2 42 3 NOT L 138 2 2 43 1 OR B 139 2 2 43 2 OR W 140 2 2 43 3 OR L 141 2 2 44 ORC 142 2 2 45 1 POP W 143 2 2 45 2 POP L 144 2 2 46 1 PUSH W 145 2 2 46 2 PUSH L 146 2 2 47 1 ROTL B 147 2 2 47 2 ROTL W 148 2 2 47 3 ROTL L 149 2 2 48 1 ROTR B 150 2 2 48 2 ROTR W 151 2 2 48 3...

Page 7: ...9 1 SUB B 177 2 2 59 2 SUB W 178 2 2 59 3 SUB L 179 2 2 60 SUBS 180 2 2 61 SUBX 181 2 2 62 TRAPA 182 2 2 63 1 XOR B 183 2 2 63 2 XOR W 184 2 2 63 3 XOR L 185 2 2 64 XORC 186 2 3 Instruction Set Summary 187 2 4 Instruction Codes 200 2 5 Operation Code Map 209 2 6 Number of States Required for Instruction Execution 212 2 7 Condition Code Modification 221 2 8 Bus cycles During Instruction Execution 2...

Page 8: ... 3 5 Reset State 244 3 6 Power Down State 244 3 6 1 Sleep Mode 244 3 6 2 Software Standby Mode 244 3 6 3 Hardware Standby Mode 244 Section 4 Basic Timing 245 4 1 Overview 245 4 2 On Chip Memory RAM ROM 245 4 3 On Chip Supporting Modules 247 4 4 External Data Bus 248 ...

Page 9: ...registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty two basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 24 ERn Register indirect with post increment or pre decrement ER...

Page 10: ...on 1 1 2 Differences from H8 300 CPU In comparison to the H8 300 CPU the H8 300H CPU has the following enhancements More general registers Eight 16 bit registers have been added Expanded address space Normal mode supports the same 64 kbyte address space as the H8 300 CPU Advanced mode supports a maximum 16 Mbyte address space Enhanced addressing The addressing modes have been enhanced to make effe...

Page 11: ...en when the corresponding general register R0 to R7 is used as an address register If the general register is referenced in the register indirect addressing mode with pre decrement Rn or post increment Rn and a carry or borrow occurs however the value in the corresponding extended register will be affected Instruction Set All additional instructions and addressing modes of the H8 300 CPU can be us...

Page 12: ...o used for the exception vector table Stack Structure When the program counter PC is pushed on the stack in a subroutine call and the PC and condition code register CCR are pushed on the stack in exception handling they are stored in the same way as in the H8 300 CPU See figure 1 3 Figure 1 3 Stack Structure normal mode H 0000 H 0001 H 0002 H 0003 H 0004 H 0005 H 0006 H 0007 H 0008 H 0009 Reset ex...

Page 13: ...ctions and addressing modes of the H8 300H can be used Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H 000000 is allocated to the exception vector table in units of 32 bits In each 32 bits the upper 8 bits are ignored and a branch address is stored in the lower 24 bits figure 1 4 The exception vector table differs depending on the microcontro...

Page 14: ...s Branch addresses can be stored in the top area from H 000000 to H 0000FF Note that this area is also used for the exception vector table Stack Structure When the program counter PC is pushed on the stack in a subroutine call and the PC and condition code register CCR are pushed on the stack in exception handling they are stored as shown in figure 1 5 Figure 1 5 Stack Structure advanced mode PC 2...

Page 15: ...1 3 Address Space Figure 1 6 shows a memory map of the H8 300H CPU Figure 1 6 Memory Map a Normal mode b Advanced mode H 0000 H FFFF H 000000 H FFFFFF 7 ...

Page 16: ... I U H U N Z V C CCR 7 6 5 4 3 2 1 0 PC 23 0 15 07 07 0 SP E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General registers Rn and extended registers En Control registers CR Legend Stack pointer Program counter Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag Negative flag Zero flag Overflow flag Carry flag SP PC CCR...

Page 17: ...o E7 and R R0 to R7 These registers are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers Figure 1 8 illustrates th...

Page 18: ...nificant PC bit is ignored When an instruction is fetched the least significant PC bit is regarded as 0 2 Condition Code Register CCR This 8 bit register contains internal CPU status information including the interrupt mask bit I and half carry H negative N zero Z overflow V and carry C flags Bit 7 Interrupt Mask Bit I Masks interrupts other than NMI when set to 1 NMI is accepted regardless of the...

Page 19: ...y occurs and cleared to 0 otherwise Used by Add instructions to indicate a carry Subtract instructions to indicate a borrow Shift and rotate instructions to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions Some instructions leave some or all of the flag bits unchanged For the action of each instruction on the flag bits ref...

Page 20: ... two digits of 4 bit BCD data 1 5 1 General Register Data Formats Figure 1 10 shows the data formats in general registers Figure 1 10 General Register Data Formats 7 6 5 4 3 2 1 0 Don t care 7 0 Don t care 7 6 5 4 3 2 1 0 4 3 7 0 7 0 Don t care Upper Lower LSB MSB LSB Data type Register number Data format 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data Byte data Byte data RnH RnL RnH RnL RnH R...

Page 21: ...r longword data at an odd address no address error occurs but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches 0 MSB LSB 15 Word data Word data Rn En 0 LSB 15 16 MSB 31 En Rn General register ER General register E General register R General register RH General register RL Most significant bit Least sign...

Page 22: ...s the stack the operand size should be word size or longword size 7 6 5 4 3 2 1 0 7 0 MSB LSB MSB LSB MSB LSB Data type Data format 1 bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M 1 Address 2N Address 2N 1 Address 2N 2 Address 2N 3 14 ...

Page 23: ...anipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR 14 BXOR BIXOR BLD BILD BST BIST Branch Bcc 2 JMP BSR JSR RTS 5 Block data transfer EEPMOV 1 Total 62 types Notes The shaded instructions are not present in the H8 300 instruction set 1 POP W Rn and PUSH W Rn are identical to MOV W SP Rn and MOV W Rn SP POP L ERn and PUSH L ERn are identical to MOV L SP ERn and MOV L ERn SP 2 Bcc is the generic de...

Page 24: ...n xx Rn ERn d 16 ERn d 24 ERn ERn ERn aa 8 aa 16 aa 24 d 8 PC d 16 PC aa 8 MOV POP PUSH MOVFPE MOVTPE ADD CMP SUB ADDX SUBX ADDS SUBS INC DEC DAA DAS MULXU DIVXU MULXS DIVXS NEG EXTU EXTS AND OR XOR NOT Data transfer Arithmetic operations Logic operations Shift Bit manipu lation BWL BWL WL B BWL BWL BWL BWL B L 1 BWL B BW BW BWL WL BWL BWL BWL B BWL B BWL BWL BWL B B BWL B BWL WL ...

Page 25: ... CPU it was word size 2 Because of its larger address space the H8 300H CPU uses a 24 bit absolute address for the JMP and JSR instructions The H8 300 CPU used 16 bits 17 Addressing Modes Function Instruction xx Rn ERn d 16 ERn d 24 ERn ERn ERn aa 8 aa 16 aa 24 d 8 PC d 16 PC aa 8 Bcc BSR JMP JSR RTS TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP EEPMOV B EEPMOV W Branch System control Block data trans...

Page 26: ... EAd Destination operand EAs Source operand CCR Condition code register N N negative bit of CCR Z Z zero bit of CCR V V overflow bit of CCR C C carry bit of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not 3 8 16 24 3 8 16 or 24 bit length Note General registers include 8 b...

Page 27: ...a 16 to a general register in synchronization with an E clock MOVTPE B Rs EAd Moves general register contents to an external memory location addressed by aa 16 in synchronization with an E clock POP W L SP Rn Pops a register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a register onto the stack PUSH W Rn is identical to MOV W Rn S...

Page 28: ...1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4 bit BCD data MULXS B W Rd Rs Rd Performs signed multiplication on data in two general registers either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits MULXU B W Rd Rs Rd Pe...

Page 29: ...he lower 16 bits of a 32 bit register to longword data by extending the sign bit EXTU W L Rd zero extension Rd Extends byte data in the lower 8 bits of a 16 bit register to word data or extends word data in the lower 16 bits of a 32 bit register to longword data by padding with zeros Logic operations AND B W L Rd Rs Rd Rd IMM Rd Performs a logical AND operation on a general register and another ge...

Page 30: ...general register BNOT B bit No of EAd bit No of EAd Inverts a specified bit in a general register or memory operand The bit number is specified by 3 bit immediate data or the lower three bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the ...

Page 31: ...s the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3 bit immediate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to th...

Page 32: ...0 BLS Low or same C Z 1 Bcc BHS Carry clear C 0 high or same BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified address JSR Bran...

Page 33: ...nsfer in other addressing modes STC B W CCR EAd Transfers the CCR contents to a destination location Byte transfer is performed in the Rd addressing mode and word transfer in other addressing modes ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically exclusive O...

Page 34: ...epeat ER5 ER6 R4 1 R4L Until R4 0 else next Transfers a data block according to parameters set in general registers R4L or R4 ER5 and R6 R4L or R4 size of block bytes ER5 starting source address R6 starting destination address Execution of the next instruction begins as soon as the transfer is completed Note Size refers to the operand size Block data transfer instruction 26 ...

Page 35: ...y 3 bits data registers by 3 bits or 4 bits Some instructions have two register fields Some have no register field Effective Address Extension Eight 16 or 32 bits specifying immediate data an absolute address or a displacement A 24 bit address or a displacement is treated as 32 bit data in which the first 8 bits are 0 Condition Field Specifies the branching condition of Bcc instructions Figure 1 1...

Page 36: ...st increment ERn Register indirect with pre decrement ERn 5 Absolute address aa 8 aa 16 aa 24 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 1 Register Direct Rn The register field of the instruction specifies an 8 16 or 32 bit general register containing the operand R0H to R7H and R0L to R7L can be specified as 8 bit registers R0 to R7 and E0 to E7 c...

Page 37: ...a memory operand The absolute address may be 8 bits long aa 8 16 bits long aa 16 or 24 bits long aa 24 For an 8 bit absolute address the upper 16 bits are all assumed to be 1 H FFFF For a 16 bit absolute address the upper 8 bits are a sign extension A 24 bit absolute address can access the entire address space Table 1 5 indicates the accessible address ranges Table 1 5 Absolute Address Access Rang...

Page 38: ...rmal mode H 000000 to H 0000FF in advanced mode In normal mode the memory operand is a word operand and the branch address is 16 bits long In advanced mode the memory operand is a longword operand The first byte is ignored and the branch address is 24 bits long Note that the first part of the address range is also the exception vector area For further details see the relevant microcontroller hardw...

Page 39: ...s EA 1 Register direct Rn op Regm Regn Operands are contents of regm and regn Register indirect ERn 2 op reg Register indirect with displacement d 16 ERn op reg disp 3 op reg Register indirect with pre decrement ERn op reg 4 Register contents Register contents Sign extension disp Register contents 1 2 or 4 Register contents 1 2 or 4 Byte Word Longword 1 2 4 Operand Size Added Value 31 0 31 0 31 0 ...

Page 40: ...ddressing Mode and Instruction Format Effective Address Calculation Effective Address EA 5 aa 8 op abs Absolute address aa 16 aa 24 op abs op abs 6 Immediate xx 8 xx 16 xx 32 23 0 8 7 H FFFF 23 0 16 15 Sign extension 23 0 Operand is immediate data op IMM ...

Page 41: ... Addressing Mode and Instruction Format disp op abs op abs op 31 0 23 0 0 23 PC contents Sign extension disp 23 0 23 0 16 15 23 0 0 23 0 23 8 7 8 7 H 0000 abs Memory contents H 00 H 0000 abs Memory contents 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 Normal mode Advanced mode 15 0 ...

Page 42: ...Legend reg regm regn General registers op Operation field disp Displacement abs Absolute address IMM Immediate data 34 ...

Page 43: ...ssembly language format of the instruction See section 2 1 1 Assembler Format Operand Size Indicates the available operand sizes Condition Code Indicates the effect of instruction execution on the flag bits in the CCR See section 2 1 3 Condition Code Description Describes the operation of the instruction in detail Available Registers Indicates which registers can be specified in the register field...

Page 44: ...ts the eight addressing modes listed next Effective address calculation is described in section 1 7 Effective Address Calculation Symbol Addressing Mode Rn Register direct ERn Register indirect d 16 ERn d 24 ERn Register indirect with displacement 16 bit or 24 bit ERn ERn Register indirect with post increment or pre decrement aa 8 16 24 Absolute address 8 bit 16 bit or 24 bit xx 8 16 32 Immediate ...

Page 45: ...C carry flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND ...

Page 46: ...pending on conditions see the notes Symbol Meaning IMM Immediate data 2 3 8 16 or 32 bits abs Absolute address 8 16 or 24 bits disp Displacement 8 16 or 24 bits rs rd rn Register number 4 bits The symbol rs corresponds to operand symbols such as Rs The symbol rd corresponds to operand symbols such as Rd The symbol rn corresponds to the operand symbol Rn ers erd ern Register number 3 bits The symbo...

Page 47: ...er it is specified by a 4 bit register field rs rd or rn The lower 3 bits specify the register number The upper bit is set to 1 to specify an extended register En or cleared to 0 to specify a general register Rn When an 8 bit register is used as a byte data register it is specified by a 4 bit register field rs rd or rn The lower 3 bits specify the register number The upper bit is set to 1 to speci...

Page 48: ...bit immediate data or by the lower 3 bits of a general register value Example 1 To set bit 3 in R2H to 1 Example 2 To load bit 5 at address H FFFF02 into the bit accumulator The operand size and addressing mode are as indicated for register or memory operand data BSET R1L R2H R1L 0 1 1 Don t care 0 0 1 R2H 1 0 1 1 0 Bit number Set to 1 BLD 5 FFFF02 H FF02 1 1 0 0 0 1 0 1 5 Load C 40 ...

Page 49: ...2 2 Instruction Descriptions The instructions are described starting in section 2 2 1 41 ...

Page 50: ...d to 0 C Set to 1 if there is a carry at bit 7 otherwise cleared to 0 I UI H U N Z V C Description This instruction adds the source operand to the contents of an 8 bit register Rd destination operand and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format...

Page 51: ...ed to 0 C Set to 1 if there is a carry at bit 15 otherwise cleared to 0 I UI H U N Z V C Description This instruction adds the source operand to the contents of a 16 bit register Rd destination operand and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st ...

Page 52: ...0 C Set to 1 if there is a carry at bit 31 otherwise cleared to 0 I UI H U N Z V C Description This instruction adds the source operand to the contents of a 32 bit register ERd destination operand and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3r...

Page 53: ...alue remains unchanged I UI H U N Z V C Description This instruction adds the immediate value 1 2 or 4 to the contents of a 32 bit register ERd Differing from the ADD instruction it does not affect the condition code flags Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct ADDS 1...

Page 54: ...rwise cleared to 0 C Set to 1 if there is a carry at bit 7 otherwise cleared to 0 I UI H U N Z V C Description This instruction adds the source operand and carry flag to the contents of an 8 bit register Rd destination register and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execut...

Page 55: ...alue remains unchanged I UI H U N Z V C 0 Description This instruction ANDs the source operand with the contents of an 8 bit register Rd destination register and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Immed...

Page 56: ...value remains unchanged I UI H U N Z V C 0 Description This instruction ANDs the source operand with the contents of a 16 bit register Rd destination register and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Immediate A...

Page 57: ...ins unchanged I UI H U N Z V C 0 Description This instruction ANDs the source operand with the contents of a 32 bit register ERd destination register and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Immediate AND...

Page 58: ...orresponding bit of the result V Stores the corresponding bit of the result C Stores the corresponding bit of the result I UI H U N Z V C Description This instruction ANDs the contents of the condition code register CCR with immediate data and stores the result in the condition code register No interrupt requests including NMI are accepted immediately after execution of this instruction Operand Fo...

Page 59: ...number is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes See the corresponding LSI hardware manual for details on the access range for aa 8 Instruction Format ...

Page 60: ... signed 8 bit or 16 bit value The branch destination address can be located in the range from 126 to 128 bytes or 32766 to 32768 bytes from the Bcc instruction Note If the immediately preceding instruction is a CMP instruction X is the destination operand and Y is the source operand Mnemonic Meaning cc Condition Signed Unsigned BRA BT Always true 0000 True BRn BF Never false 0001 False BHI HIgh 00...

Page 61: ... disp 4 d 16 5 8 7 0 disp 6 d 8 4 8 disp 4 d 16 5 8 8 0 disp 6 d 8 4 9 disp 4 d 16 5 8 9 0 disp 6 d 8 4 A disp 4 d 16 5 8 A 0 disp 6 d 8 4 B disp 4 d 16 5 8 B 0 disp 6 d 8 4 C disp 4 d 16 5 8 C 0 disp 6 d 8 4 D disp 4 d 16 5 8 D 0 disp 6 d 8 4 E disp 4 d 16 5 8 E 0 disp 6 d 8 4 F disp 4 d 16 5 8 F 0 disp 6 Addressing Mode Mnemonic Operands Program counter relative Program counter relative Program ...

Page 62: ...ue remains unchanged C Previous value remains unchanged I UI H U N Z V C Description This instruction clears a specified bit in the destination operand to 0 The bit number can be specified by 3 bit immediate data or by the lower three bits of a general register Rn The specified bit is not tested The condition code flags are not altered Available Registers Rd R0L to R7L R0H to R7H Rn R0L to R7L R0H...

Page 63: ...ntroller hardware manual Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct BCLR xx 3 Rd 7 2 0 IMM rd 2 Register indirect BCLR xx 3 ERd 7 D 0 erd 0 7 2 0 IMM 0 8 Absolute address BCLR xx 3 aa 8 7 F abs 7 2 0 IMM 0 8 Register direct BCLR Rn Rd 6 2 rn rd 2 Register indirect BCLR Rn ERd 7 D 0 erd 0 6 2 rn 0 8 Absolute address BCLR Rn aa 8 7 F abs 6 2 rn 0 8 No of States Addressing...

Page 64: ... The bit number is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual C C 7 0 Speci...

Page 65: ... is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual Instruction Format 1st byte ...

Page 66: ... bit The bit number is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual C C 7 0 S...

Page 67: ...pecified by 3 bit immediate data Other bits in the destination operand remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual C 7 0 Specified by xx 3 Bit ...

Page 68: ...n the carry bit The bit number is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manua...

Page 69: ...y 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual Specified by xx 3 C 0 7 Bit No EAd Instruct...

Page 70: ...Previous value remains unchanged C Previous value remains unchanged I UI H U N Z V C Description This instruction inverts a specified bit in the destination operand The bit number is specified by 3 bit immediate data or by the lower 3 bits of a general register The specified bit is not tested The condition code remains unchanged Available Registers Rd R0L to R7L R0H to R7H Rn R0L to R7L R0H to R7H...

Page 71: ...roller hardware manual Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct BNOT xx 3 Rd 7 1 0 IMM rd 2 Register indirect BNOT xx 3 ERd 7 D 0 erd 0 7 1 0 IMM 0 8 Absolute address BNOT xx 3 aa 8 7 F abs 7 1 0 IMM 0 8 Register direct BNOT Rn Rd 6 1 rn rd 2 Register indirect BNOT Rn ERd 7 D 0 erd 0 6 1 rn 0 8 Absolute address BNOT Rn aa 8 7 F abs 6 1 rn 0 8 No of States Addressing M...

Page 72: ...e bit number is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual C C 7 0 Specifie...

Page 73: ...lue remains unchanged C Previous value remains unchanged I UI H U N Z V C Description This instruction sets a specified bit in the destination operand to 1 The bit number can be specified by 3 bit immediate data or by the lower three bits of a general register The specified bit is not tested The condition code flags are not altered Available Registers Rd R0L to R7L R0H to R7H Rn R0L to R7L R0H to ...

Page 74: ... EAd is byte data in a register or on memory Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct BSET xx 3 Rd 7 0 0 IMM rd 2 Register indirect BSET xx 3 ERd 7 D 0 erd 0 7 0 0 IMM 0 8 Absolute address BSET xx 3 aa 8 7 F abs 7 0 0 IMM 0 8 Register direct BSET Rn Rd 6 0 rn rd 2 Register indirect BSET Rn ERd 7 D 0 erd 0 6 0 rn 0 8 Absolute address BSET Rn aa 8 7 F abs 6 0 rn 0 8 No ...

Page 75: ...ss The PC value pushed onto the stack is the address of the instruction following the BSR instruction The displacement is a signed 8 bit or 16 bit value so the possible branching range is 126 to 128 bytes or 32766 to 32768 bytes from the address of the BSR instruction Operand Format and Number of States Required for Execution Notes The stack structure differs between normal mode and advanced mode ...

Page 76: ...d by 3 bit immediate data Other bits in the destination operand remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual C 7 0 Specified by xx 3 Bit No EAd ...

Page 77: ...s value remains unchanged C Previous value remains unchanged I UI H U N Z V C Description This instruction tests a specified bit in the destination operand and sets or clears the Z flag according to the result The bit number can be specified by 3 bit immediate data or by the lower three bits of a general register The destination operand remains unchanged Available Registers Rd R0L to R7L R0H to R7...

Page 78: ...troller hardware manual Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct BTST xx 3 Rd 7 3 0 IMM rd 2 Register indirect BTST xx 3 ERd 7 C 0 erd 0 7 3 0 IMM 0 6 Absolute address BTST xx 3 aa 8 7 E abs 7 3 0 IMM 0 6 Register direct BTST Rn Rd 6 3 rn rd 2 Register indirect BTST Rn ERd 7 C 0 erd 0 6 3 rn 0 6 Absolute address BTST Rn aa 8 7 E abs 6 3 rn 0 6 No of States Addressing ...

Page 79: ...arry bit The bit number is specified by 3 bit immediate data The destination operand contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note The addressing mode is the addressing mode of the destination operand EAd Notes For the aa 8 access range refer to the relevant microcontroller hardware manual C C 7...

Page 80: ...a borrow at bit 7 otherwise cleared to 0 I UI H U N Z V C Description This instruction subtracts the source operand from the contents of an 8 bit register Rd destination register and sets or clears the CCR bits according to the result The destination register contents remain unchanged Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required...

Page 81: ...row at bit 15 otherwise cleared to 0 I UI H U N Z V C Description This instruction subtracts the source operand from the contents of a 16 bit register Rd destination register and sets or clears the CCR bits according to the result The contents of the 16 bit register Rd remain unchanged Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Ex...

Page 82: ...here is a borrow at bit 31 otherwise cleared to 0 I H N Z V C Description This instruction subtracts the source operand from the contents of a 32 bit register ERd destination register and sets or clears the CCR bits according to the result The contents of the 32 bit register ERd remain unchanged Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Exec...

Page 83: ...of an addition operation performed by an ADD B or ADDX instruction on 4 bit BCD data is contained in an 8 bit register Rd destination register and the carry and half carry flags the DAA instruction adjusts the general register contents by adding H 00 H 06 H 60 or H 66 according to the table below C Flag Upper 4 Bits H Flag Lower 4 Bits C Flag before before before before after Adjustment Adjustment...

Page 84: ...red for Execution Notes Valid results 8 bit register Rd contents and C V Z N and H flags are not assured if this instruction is executed under conditions other than those described above Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct DAA Rd 0 F 0 rd 2 No of States Addressing Mode Mnemonic Operands 76 ...

Page 85: ...to R7L R0H to R7H C Flag Upper 4 Bits H Flag Lower 4 Bits C Flag before before before before after Adjustment Adjustment Adjustment Adjustment Adjustment 0 0 to 9 0 0 to 9 00 0 0 0 to 8 1 6 to F FA 0 1 7 to F 0 0 to 9 A0 1 1 6 to F 1 6 to F 9A 1 Value Added hexadecimal Operation Rd decimal adjust Rd Assembly Language Format DAS Rd Operand Size Byte Condition Code H Undetermined no guaranteed value...

Page 86: ...tes Valid results 8 bit register Rd contents and C V Z N and H flags are not assured if this instruction is executed under conditions other than those described above Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct DAS Rd 1 F 0 rd 2 No of States Addressing Mode Mnemonic Operands 78 ...

Page 87: ...lue in Rd was H 80 otherwise cleared to 0 C Previous value remains unchanged I UI H U N Z V C Description This instruction decrements an 8 bit register Rd destination register and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes An overflow is caused by the operation H 80 1 H 7F Instruction Form...

Page 88: ... value remains unchanged I UI H U N Z V C Description This instruction subtracts the immediate value 1 or 2 from the contents of a 16 bit register Rd destination register and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes An overflow is caused by the operations H 8000 1 H 7FFF H 8000 2 H 7FFE and...

Page 89: ... UI H U N Z V C Description This instruction subtracts the immediate value 1 or 2 from the contents of a 32 bit register ERd destination register and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes An overflow is caused by the operations H 80000000 1 H 7FFFFFFF H 80000000 2 H 7FFFFFFE and H 80000001 2 ...

Page 90: ...ts of Rd Valid results are not assured if division by zero is attempted or an overflow occurs For information on avoiding overflow see DIVXS Instruction Zero Divide and Overflow Available Registers Rd R0 to R7 E0 to E7 Rs R0L to R7L R0H to R7H Rd Rs Rd Dividend Divisor Remainder Quotient 16 bits 8 bits 8 bits 8 bits Operation Rd Rs Rd Assembly Language Format DIVXS B Rs Rd Operand Size Byte Condit...

Page 91: ...ag is set to 1 if the dividend and divisor have different signs and cleared to 0 if they have the same sign The N flag may therefore be set to 1 when the quotient is zero Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct DIVXS B Rs Rd 0 1 D 0 5 1 rs rd 16 No of States Addressing Mode Mnemonic Operands 83 ...

Page 92: ...in the upper 16 bits Ed Valid results are not assured if division by zero is attempted or an overflow occurs For information on avoiding overflow see DIVXS Instruction Zero Divide and Overflow Available Registers ERd ER0 to ER7 Rs R0 to R7 E0 to E7 ERd Rs ERd Dividend Divisor Remainder Quotient 32 bits 16 bits 16 bits 16 bits Operation ERd Rs ERd Assembly Language Format DIVXS W Rs ERd Operand Siz...

Page 93: ... is set to 1 if the dividend and divisor have different signs and cleared to 0 if they have the same sign The N flag may therefore be set to 1 when the quotient is zero Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct DIVXS W Rs ERd 0 1 D 0 5 3 rs 0 erd 24 No of States Addressing Mode Mnemonic Operands 85 ...

Page 94: ...R bit 4 to 1 L1 MOV W R1 R1 Test dividend BPL L2 Branch to L2 if N flag 0 positive dividend NEG W R1 Take 2 s complement of R1 to make sign positive XORC 50 CCR Invert CCR bits 6 and 4 L2 MOV B R1H R2L EXTU W R2 DIVXU B R0L R2 Use DIVXU B instruction to divide non negative dividend MOV B R2H R1H by positive divisor DIVXU B R0L R1 16 bits 8 bits quotient 16 bits and remainder 8 bits MOV B R2L R2H S...

Page 95: ...t dividend to 32 bits and then use DIVXS to divide EXTS W R0 BEQ ZERODIV EXTS L ER1 DIVXS L R0 ER1 RTS ZERODIV This program leaves the 16 bit quotient in R1 and the 8 bit remainder in E1 in a 16 bit sign extended format 87 R1 ROL ER1 ER1 R0L Dividend Divisor Sign extension Divisor Dividend Sign extension Quotient Remainder ...

Page 96: ...make sign positive XORC 50 CCR Invert CCR bits 6 and 4 L2 MOV W E1 R2 EXTU L ER2 DIVXU W R0 E2 Use DIVXU W instruction to divide non negative dividend MOV W E2 R1 by positive divisor DIVXU W R0 ER1 32 bits 16 bits quotient 32 bits and remainder MOV W R2 E2 16 bits MOV W R1 R2 See DIVXU Instruction Zero Divide and Overflow STC CCR R1L Copy CCR contents to R1L BTST 6 R1L Test CCR bit 6 BEQ L3 Branch...

Page 97: ...nsigned division result of the DIVXU instruction as shown next UI U Divisor Dividend Remainder Quotient Sign Modification 0 0 Positive Positive Positive Positive No sign modification 0 1 Negative Positive Positive Negative Sign of quotient is reversed 1 0 Negative Negative Negative Positive Sign of remainder is reversed 1 1 Positive Negative Negative Negative Signs of quotient and remainder are bo...

Page 98: ...result in the 16 bit register Rd The division is unsigned The operation performed is 16 bits 8 bits 8 bit quotient and 8 bit remainder The quotient is placed in the lower 8 bits of Rd The remainder is placed in the upper 8 bits of Rd Valid results are not assured if division by zero is attempted or an overflow occurs For information on avoiding overflow see DIVXU Instruction Zero Divide and Overfl...

Page 99: ...e 32 bit register ERd The division is unsigned The operation performed is 32 bits 16 bits 16 bit quotient and 16 bit remainder The quotient is placed in the lower 16 bits Rd of the 32 bit register ERd The remainder is placed in the upper 8 bits of Ed Valid results are not assured if division by zero is attempted or an overflow occurs For information on avoiding overflow see DIVXU Instruction Zero ...

Page 100: ...extend to 16 bits DIVXU B R0L R2 2 Divide upper 8 bits of dividend MOV B R2H R1H 3 R2H R1H store partial remainder in R1H DIVXU B R0L R1 4 Divide lower 8 bits of dividend including repeated division of upper 8 bits MOV B R2L R2H Store upper part of quotient in R2H MOV B R1L R2L 5 Store lower part of quotient in R2L RTS ZERODIV Zero divide handling routine The resulting operation is 16 bits 8 bits ...

Page 101: ...bit dividend to 32 bits EXTU W R0 ER1 Divide using DIVXU W RTS ZERODIV Zero divide handling routine Instead of 16 bits 8 bits the operation performed is 32 bits 16 bits quotient 16 bits and remainder 16 bits and no overflow occurs The 16 bit quotient is stored in R1 and the 8 bit remainder in the lower 8 bits of E1 The upper 8 bits of E1 are all 0 ER1 R0L R1 ER1 Divisor Dividend Sign extension Sig...

Page 102: ... partial remainder in E1 DIVXU W R0 ER1 4 Divide lower 16 bits of dividend including repeated division of upper 16 bits MOV W R2 E2 Store upper part of quotient in E2 MOV W R1 R2 5 Store lower part of quotient in R2 RTS ZERODIV Zero divide handling routine The resulting operation is 32 bits 16 bits quotient 32 bits and remainder 16 bits and no overflow occurs The 32 bit quotient is stored in ER2 t...

Page 103: ...d while the block transfer is in progress When the EEPMOV instruction ends R4L contains 0 and ER5 and ER6 contain the last transfer address 1 The data transfer is performed a byte at a time with R4L indicating the number of bytes to be transferred The byte symbol in the assembly language format designates the size of R4L and limits the maximum number of bytes that can be transferred to 255 Operand...

Page 104: ...ruction No interrupts except NMI are detected while the block transfer is in progress When the EEPMOV instruction ends R4 contains 0 and ER5 and ER6 contain the last transfer address 1 The data transfer is performed a byte at a time with R4 indicating the number of bytes to be transferred The word symbol in the assembly language format designates the size of R4 allowing a maximum 65535 bytes to be...

Page 105: ...of the next byte to be transferred ER6 destination address of the next byte R4 number of bytes remaining to be transferred The program counter value pushed on the stack in NMI interrupt exception handling is the address of the next instruction after the EEPMOV W instruction Programs should be coded as follows to allow for NMI interrupts during execution of the EEPMOV W instruction Example L1 EEPMO...

Page 106: ...s value remains unchanged I UI H U N Z V C 0 Description This instruction copies the sign of the lower 8 bits in a 16 bit register Rd in the upward direction copies Rd bit 7 to bits 15 to 8 to extend the data to signed word data Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Don t care Rd 8 bits Sign bit 8 bits Sign extension Rd 8 bits 8 b...

Page 107: ...revious value remains unchanged I UI H U N Z V C 0 Description This instruction copies the sign of the lower 16 bits general register Rd in a 32 bit register ERd in the upward direction copies ERd bit 15 to bits 31 to 16 to extend the data to signed longword data Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes Don t care ERd 16 bits Sign bit 16 b...

Page 108: ...remains unchanged I UI H U N Z V C 0 0 Description This instruction extends the lower 8 bits in a 16 bit register Rd to word data by padding with zeros That is it clears the upper 8 bits of Rd bits 15 to 8 to 0 Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Don t care Rd 8 bits 8 bits Zero extension Rd 8 bits 8 bits Instruction Format 1st ...

Page 109: ...nged I UI H U N Z V C 0 0 Description This instruction extends the lower 16 bits general register Rd in a 32 bit register ERd to longword data by padding with zeros That is it clears the upper 16 bits of ERd bits 31 to 16 to 0 Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes Don t care ERd 16 bits 16 bits Zero extension ERd 16 bits 16 bits Instruc...

Page 110: ...s otherwise cleared to 0 C Previous value remains unchanged I UI H U N Z V C Description This instruction increments an 8 bit register Rd destination register and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes An overflow is caused by the operation H 7F 1 H 80 Instruction Format 1st byte 2nd b...

Page 111: ...F 2 H 8001 and H 7FFE 2 H 8000 Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct INC W 1 Rd 0 B 5 rd 2 Register direct INC W 2 Rd 0 B D rd 2 No of States Addressing Mode Mnemonic Operands Operation Rd 1 Rd Rd 2 Rd Assembly Language Format INC W 1 Rd INC W 2 Rd Operand Size Word Condition Code H Previous value remains unchanged N Set to 1 if the result is negative otherwise cle...

Page 112: ...d I UI H U N Z V C Description This instruction adds the immediate value 1 or 2 to the contents of a 32 bit register ERd destination register and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes An overflow is caused by the operations H 7FFFFFFF 1 H 80000000 H 7FFFFFFF 2 H 80000001 and H 7FFFFFFE 2 H 80...

Page 113: ...tion branches unconditionally to a specified address Available Registers ERn ER0 to ER7 Operand Format and Number of States Required for Execution Notes The structure of the branch address and the number of states required for execution differ between normal mode and advanced mode The branch address must be even Instruction Format No of State 1st byte 2nd byte 3rd byte 4th byte Normal Advanced Reg...

Page 114: ...nstruction pushes the program counter on the stack as a return address then branches to a specified effective address The program counter value pushed on the stack is the address of the instruction following the JSR instruction Available Registers ERn ER0 to ER7 Operand Format and Number of States Required for Execution Instruction Format No of State 1st byte 2nd byte 3rd byte 4th byte Normal Adva...

Page 115: ...that the structures of the stack and branch addresses differ between normal and advanced mode Only the lower 16 bits of the PC are saved in normal mode The branch address must be even 107 PC 23 16 15 8 7 0 Normal mode PC 23 16 15 8 7 0 Advanced mode Reserved ...

Page 116: ...rom the corresponding bit in the source operand C Loaded from the corresponding bit in the source operand I UI H U N Z V C Description This instruction loads the source operand into the CCR Note that no interrupts even NMI interrupts will be accepted at the point that this instruction completes Available Registers Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution ...

Page 117: ...m the corresponding bit in the source operand V Loaded from the corresponding bit in the source operand C Loaded from the corresponding bit in the source operand I UI H U N Z V C Description This instruction loads the source operand contents into the condition code register CCR Although CCR is a byte register the source operand is word size The contents of the even address are loaded into CCR No i...

Page 118: ...h byte 9th byte 10th byte Register indirect Register indirect with displacement Register indirect with post increment LDC W LDC W LDC W LDC W LDC W LDC W ERs CCR d 16 ERs CCR d 24 ERs CCR ERs CCR aa 16 CCR aa 24 CCR Absolute address 0 0 0 0 0 0 1 1 1 1 1 1 4 4 4 4 4 4 0 0 0 0 0 0 6 6 7 6 6 6 9 F 8 D B B ers ers ers ers 0 0 0 0 0 0 0 0 0 0 6 B 2 0 0 disp abs abs 0 0 0 2 disp 6 8 12 8 8 10 0 2 2 34 ...

Page 119: ...s value remains unchanged I UI H U N Z V C 0 Description This instruction transfers one byte of data from an 8 bit register Rs to an 8 bit register Rd tests the transferred data and sets condition code flags according to the result Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd b...

Page 120: ...vious value remains unchanged I UI H U N Z V C 0 Description This instruction transfers one word of data from a 16 bit register Rs to a 16 bit register Rd tests the transferred data and sets condition code flags according to the result Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte ...

Page 121: ...Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers one longword of data from a 32 bit register ERs to a 32 bit register ERd tests the transferred data and sets condition code flags according to the result Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd...

Page 122: ...ve otherwise cleared to 0 Z Set to 1 if the data value is zero otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers the source operand contents to an 8 bit register Rs tests the transferred data and sets condition code flags according to the result Available Registers Rd R0L to R7L R0H to R7H ERs ER0 to ER7 114 ...

Page 123: ...manual No of States Mnemonic Operands Addressing Mode Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Immediate Register indirect with displacement Register indirect with post increment MOV B MOV B MOV B MOV B MOV B MOV B xx 8 Rd d 16 ERs Rd d 24 ERs Rd ERs Rd aa 8 Rd aa 16 Rd Absolute address F 6 6 7 6 2 6 6 rd 8 E 8 C rd A A ers ers ers ers 0 0 0 0 6 A ...

Page 124: ...tive otherwise cleared to 0 Z Set to 1 if the data value is zero otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers the source operand contents to a 16 bit register Rd tests the transferred data and sets condition code flags according to the result Available Registers Rd R0 to R7 E0 to E7 ERs ER0 to ER7 116 ...

Page 125: ...n Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Immediate Register indirect with displacement Register indirect with post increment MOV W MOV W MOV W MOV W MOV W MOV W xx 16 Rd d 16 ERs Rd d 24 ERs Rd ERs Rd aa 16 Rd abs aa 24 Rd abs Absolute address 7 6 6 7 6 6 6 9 9 F 8 D B B 2 0 0 disp 0 0 2 rd rd rd 0 rd rd rd 6 0 B 0 disp 4 4 6 10 6 6 8 rd Register indirect MO...

Page 126: ...d to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers the source operand contents to a specified 32 bit register ERd tests the transferred data and sets condition code flags according to the result The first memory word located at the effective address is stored in extended register Ed The next word is stored in general register R...

Page 127: ... byte 6th byte 7th byte 8th byte 9th byte 10th byte MOV L MOV L MOV L MOV L disp MOV L MOV L MOV L aa 24 ERd xx 32 Rd IMM ERs ERd d 16 ERs ERd d 24 ERs ERd ERs ERd aa 16 ERd 7 0 0 0 0 0 0 A 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 7 6 6 6 9 F 8 D B B ers ers ers ers 0 0 0 0 0 0 0 0 0 erd erd erd erd erd 6 0 B 0 2 0 0 abs erd 0 abs 0 2 ers 0 0 disp 6 8 10 14 10 10 12 Immediate Register indirect wi...

Page 128: ...cleared to 0 Z Set to 1 if the data value is zero otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers the contents of an 8 bit register Rs source operand to a destination location tests the transferred data and sets condition code flags according to the result Available Registers Rs R0L to R7L R0H to R7H ERd ER0 ...

Page 129: ...s the designated part RnL or RnH of the resulting ERn value No of States Mnemonic Operands Addressing Mode Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Register indirect Register indirect with displacement Register indirect with pre decrement MOV B MOV B MOV B MOV B MOV B MOV B Rs ERd Rs d 16 ERd Rs d 24 ERd Rs ERd Rs aa 8 Rs aa 16 Absolute address 6 6...

Page 130: ...e cleared to 0 Z Set to 1 if the data value is zero otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers the contents of a 16 bit register Rs source operand to a destination location tests the transferred data and sets condition code flags according to the result Available Registers Rs R0 to R7 E0 to E7 ERd ER0 to...

Page 131: ...ing value No of States Mnemonic Operands Addressing Mode Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Register indirect Register indirect with displacement Register indirect with post increment MOV W MOV W MOV W MOV W MOV W Rs ERd Rs d 16 ERd Rs d 24 ERd Rs ERd Rs aa 16 6 6 7 6 6 6 9 F 8 D B B erd erd erd erd 1 1 0 1 6 B A 0 0 disp abs abs 0 0 disp 4 6...

Page 132: ...ared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction transfers the contents of a 32 bit register ERs source operand to a destination location tests the transferred data and sets condition code flags according to the result The extended register Es contents are stored at the first word indicated by the effective address The general register Rs contents are st...

Page 133: ...essing Mode Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Register indirect Register indirect with displacement Register indirect with pre decrement MOV L MOV L MOV L MOV L MOV L MOV L ERs ERd ERs d 16 ERd ERs d 24 ERd ERs ERd ERs aa 16 ERs aa 24 Absolute address 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 6 6 7 6 6 6 9 F 8 D B B ...

Page 134: ...nization with an E clock tests the transferred data and sets condition code flags according to the result Note Avoid using this instruction in microcontrollers not having an E clock output pin or in single chip mode Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes 1 This instruction cannot be used with addressing modes other than the abo...

Page 135: ...address in synchronization with an E clock tests the transferred data and sets condition code flags according to the result Note Avoid using this instruction in microcontrollers not having an E clock output pin or in single chip mode Available Registers Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes 1 This instruction cannot be used with addressing modes ...

Page 136: ...t register Rd destination operand by the contents of an 8 bit register Rs source operand as signed data and stores the result in the 16 bit register Rd If Rd is a general register Rs can be the upper part RdH or lower part RdL of Rd The operation performed is 8 bit 8 bit 16 bit signed multiplication Available Registers Rd R0 to R7 E0 to E7 Rs R0L to R7L R0H to R7H Operand Format and Number of Stat...

Page 137: ... bits of a 32 bit register ERd destination operand by the contents of a 16 bit register Rs source operand as signed data and stores the result in the 32 bit register ERd Rs can be the upper part Ed or lower part Rd of ERd The operation performed is 16 bit 16 bit 32 bit signed multiplication Available Registers ERd ER0 to ER7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Exe...

Page 138: ... Rd destination operand by the contents of an 8 bit register Rs source operand and stores the result in the 16 bit register Rd If Rd is a general register Rs can be the upper part RdH or lower part RdL of Rd The operation performed is 8 bit 8 bit 16 bit multiplication Available Registers Rd R0 to R7 E0 to E7 Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes ...

Page 139: ...32 bit register ERd destination operand by the contents of a 16 bit register Rs source operand and stores the result in the 32 bit register ERd Rs can be the upper part Ed or lower part Rd of ERd The operation performed is 16 bit 16 bit 32 bit multiplication Available Registers ERd ER0 to ER7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes ERd Rs ERd Don t car...

Page 140: ... cleared to 0 I UI H U N Z V C Description This instruction takes the two s complement of the contents of an 8 bit register Rd destination operand and stores the result in the 8 bit register Rd subtracting the register contents from H 00 If the original contents of Rd was H 80 however the result remains H 80 Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required ...

Page 141: ...leared to 0 I UI H U N Z V C Description This instruction takes the two s complement of the contents of a 16 bit register Rd destination operand and stores the result in the 16 bit register Rd subtracting the register contents from H 0000 If the original contents of Rd was H 8000 however the result remains H 8000 Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required...

Page 142: ...d to 0 I UI H U N Z V C Description This instruction takes the two s complement of the contents of a 32 bit register ERd destination operand and stores the result in the 32 bit register ERd subtracting the register contents from H 00000000 If the original contents of ERd was H 80000000 however the result remains H 80000000 Available Registers ERd ER0 to ER7 Operand Format and Number of States Requ...

Page 143: ...alue remains unchanged C Previous value remains unchanged I UI H U N Z V C Description This instruction only increments the program counter causing the next instruction to be executed The internal state of the CPU does not change Available Registers Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte NOP 0 0 0 0 2 No of States Add...

Page 144: ... 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction takes the one s complement of the contents of an 8 bit register Rd destination operand and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4t...

Page 145: ...herwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction takes the one s complement of the contents of a 16 bit register Rd destination operand and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd b...

Page 146: ...ro otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction takes the one s complement of the contents of a 32 bit register ERd destination operand and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd ...

Page 147: ...us value remains unchanged I UI H U N Z V C 0 Description This instruction ORs the source operand with the contents of an 8 bit register Rd destination register and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Im...

Page 148: ...ous value remains unchanged I UI H U N Z V C 0 Description This instruction ORs the source operand with the contents of a 16 bit register Rd destination register and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Immediat...

Page 149: ...remains unchanged I UI H U N Z V C 0 Description This instruction ORs the source operand with the contents of a 32 bit register ERd destination register and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Immediate ...

Page 150: ...he corresponding bit of the result V Stores the corresponding bit of the result C Stores the corresponding bit of the result I UI H U N Z V C Description This instruction ORs the contents of the condition code register CCR with immediate data and stores the result in the condition code register No interrupt requests including NMI are accepted immediately after execution of this instruction Operand...

Page 151: ...leared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction restores data from the stack to a 16 bit general register Rn tests the restored data and sets condition code flags according to the result Available Registers Rn R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes POP W Rn is identical to MOV W SP Rn Instruction Format 1st ...

Page 152: ...ared to 0 C Previous value remains unchanged I UI H U N Z V C 0 Description This instruction restores data from the stack to a 32 bit general register ERn tests the restored data and sets condition code flags according to the result Available Registers ERn ER0 to ER7 Operand Format and Number of States Required for Execution Notes POP L ERn is identical to MOV L SP ERn Instruction Format 1st byte ...

Page 153: ...tion This instruction saves data from a 16 bit register Rn onto the stack tests the saved data and sets condition code flags according to the result Available Registers Rn R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes 1 PUSH W Rn is identical to MOV W Rn SP 2 When PUSH W R7 or PUSH W E7 is executed the value saved on the stack is the lower part R7 or upper part...

Page 154: ... H U N Z V C 0 Description This instruction pushes data from a 32 bit register ERn onto the stack tests the saved data and sets condition code flags according to the result Available Registers ERn ER0 to ER7 Operand Format and Number of States Required for Execution Notes 1 PUSH L ERn is identical to MOV L ERn SP 2 When PUSH L ER7 is executed the value saved on the stack is the value of ER7 before...

Page 155: ...previous value in bit 7 I UI H U N Z V C 0 Description This instruction rotates the bits in an 8 bit register Rd destination register one bit to the left The most significant bit is rotated to the least significant bit bit 0 and also copied to the carry flag Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes MSB LSB C b7 b0 Instruction For...

Page 156: ... previous value in bit 15 I UI H U N Z V C 0 Description This instruction rotates the bits in a 16 bit register Rd destination register one bit to the left The most significant bit is rotated to the least significant bit bit 0 and also copied to the carry flag Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes MSB LSB C b15 b0 Instruction Form...

Page 157: ... the previous value in bit 31 I UI H U N Z V C 0 Description This instruction rotates the bits in a 32 bit register ERd destination register one bit to the left The most significant bit is rotated to the least significant bit bit 0 and also copied to the carry flag Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes MSB LSB C b31 b0 Instruction Forma...

Page 158: ... previous value in bit 0 I UI H U N Z V C 0 Description This instruction rotates the bits in an 8 bit register Rd destination register one bit to the right The least significant bit is rotated to the most significant bit bit 7 and also copied to the carry flag Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes MSB LSB b7 b0 C Instruction F...

Page 159: ...e previous value in bit 0 I UI H U N Z V C 0 Description This instruction rotates the bits in a 16 bit register Rd destination register one bit to the right The least significant bit is rotated to the most significant bit bit 15 and also copied to the carry flag Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes MSB LSB b15 b0 C Instruction Fo...

Page 160: ...s the previous value in bit 0 I UI H U N Z V C 0 Description This instruction rotates the bits in a 32 bit register ERd destination register one bit to the right The least significant bit is rotated to the most significant bit bit 31 and also copied to the carry flag Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes MSB LSB b31 b0 C Instruction For...

Page 161: ...ives the previous value in bit 7 I UI H U N Z V C 0 Description This instruction rotates the bits in an 8 bit register Rd destination register one bit to the left through the carry flag The carry flag is rotated into the least significant bit bit 0 The most significant bit rotates into the carry flag Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Exec...

Page 162: ...eives the previous value in bit 15 I UI H U N Z V C 0 Description This instruction rotates the bits in a 16 bit register Rd destination register one bit to the left through the carry flag The carry flag is rotated into the least significant bit bit 0 The most significant bit rotates into the carry flag Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execut...

Page 163: ... Receives the previous value in bit 31 I UI H U N Z V C 0 Description This instruction rotates the bits in a 32 bit register ERd destination register one bit to the left through the carry flag The carry flag is rotated into the least significant bit bit 0 The most significant bit rotates into the carry flag Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Executi...

Page 164: ...eives the previous value in bit 0 I UI H U N Z V C 0 Description This instruction rotates the bits in an 8 bit register Rd destination register one bit to the right through the carry flag The carry flag is rotated into the most significant bit bit 7 The least significant bit rotates into the carry flag Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Ex...

Page 165: ...ceives the previous value in bit 0 I UI H U N Z V C 0 Description This instruction rotates the bits in a 16 bit register Rd destination register one bit to the right through the carry flag The carry flag is rotated into the most significant bit bit 15 The least significant bit rotates into the carry flag Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Exec...

Page 166: ...C Receives the previous value in bit 0 I UI H U N Z V C 0 Description This instruction rotates the bits in a 32 bit register ERd destination register one bit to the right through the carry flag The carry flag is rotated into the most significant bit bit 31 The least significant bit rotates into the carry flag Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execu...

Page 167: ...stored from the corresponding bit on the stack I UI H U N Z V C Description This instruction returns from an exception handling routine by restoring the condition code register CCR and program counter PC from the stack Program execution continues from the address restored to the program counter The CCR and PC contents at the time of execution of this instruction are lost Operand Format and Number ...

Page 168: ... Program execution continues from the address restored to the program counter The PC contents at the time of execution of this instruction are lost Available Registers Operand Format and Number of States Required for Execution Notes The stack structure and number of states required for execution differ between normal mode and advanced mode In normal mode only the lower 16 bits of the program count...

Page 169: ...alue in bit 7 I UI H U N Z V C Description This instruction shifts the bits in an 8 bit register Rd destination operand one bit to the left The most significant bit shifts into the carry flag The least significant bit bit 0 is cleared to 0 Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes The SHAL instruction differs from the SHLL instruc...

Page 170: ...value in bit 15 I UI H U N Z V C Description This instruction shifts the bits in a 16 bit register Rd destination operand one bit to the left The most significant bit shifts into the carry flag The least significant bit bit 0 is cleared to 0 Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes The SHAL instruction differs from the SHLL instructi...

Page 171: ...ous value in bit 31 I UI H U N Z V C Description This instruction shifts the bits in a 32 bit register ERd destination operand one bit to the left The most significant bit shifts into the carry flag The least significant bit bit 0 is cleared to 0 Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes The SHAL instruction differs from the SHLL instructio...

Page 172: ... cleared to 0 C Receives the previous value in bit 0 I UI H U N Z V C 0 Description This instruction shifts the bits in an 8 bit register Rd destination operand one bit to the right Bit 0 shifts into the carry flag Bit 7 shifts into itself Since bit 7 remains unaltered the sign does not change Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution N...

Page 173: ... cleared to 0 C Receives the previous value in bit 0 I UI H U N Z V C 0 Description This instruction shifts the bits in a 16 bit register Rd destination operand one bit to the right Bit 0 shifts into the carry flag Bit 15 shifts into itself Since bit 15 remains unaltered the sign does not change Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Not...

Page 174: ...wise cleared to 0 C Receives the previous value in bit 0 I UI H U N Z V C 0 Description This instruction shifts the bits in a 32 bit register ERd destination operand one bit to the right Bit 0 shifts into the carry flag Bit 31 shifts into itself Since bit 31 remains unaltered the sign does not change Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Note...

Page 175: ...N Z V C 0 Description This instruction shifts the bits in an 8 bit register Rd destination operand one bit to the left The most significant bit shifts into the carry flag The least significant bit bit 0 is cleared to 0 Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes The SHLL instruction differs from the SHAL instruction in its effect on...

Page 176: ...U N Z V C 0 Description This instruction shifts the bits in a 16 bit register Rd destination operand one bit to the left The most significant bit shifts into the carry flag The least significant bit bit 0 is cleared to 0 Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes The SHLL instruction differs from the SHAL instruction in its effect on t...

Page 177: ...I H U N Z V C 0 Description This instruction shifts the bits in a 32 bit register ERd destination operand one bit to the left The most significant bit shifts into the carry flag The least significant bit bit 0 is cleared to 0 Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes The SHLL instruction differs from the SHAL instruction in its effect on th...

Page 178: ...eceives the previous value in bit 0 I UI H U N Z V C 0 0 Description This instruction shifts the bits in an 8 bit register Rd destination operand one bit to the right The least significant bit shifts into the carry flag The most significant bit bit 7 is cleared to 0 Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes LSB MSB b7 b0 0 C Instr...

Page 179: ...us value in bit 0 I UI H U N Z V C 0 0 Description This instruction shifts the bits in a 16 bit register Rd destination operand one bit to the right The least significant bit shifts into the carry flag The most significant bit bit 15 is cleared to 0 Available Registers Rd R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes LSB MSB b15 b0 0 C Instruction Format 1st by...

Page 180: ...evious value in bit 0 I UI H U N Z V C 0 0 Description This instruction shifts the bits in a 32 bit register ERd destination operand one bit to the right The least significant bit shifts into the carry flag The most significant bit bit 31 is cleared to 0 Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes LSB MSB b31 b0 0 C Instruction Format 1st byt...

Page 181: ...ternal state remains unchanged but the CPU stops executing instructions and waits for an exception handling request When it receives an exception handling request the CPU exits the power down state and begins the exception handling sequence Interrupt requests other than NMI cannot end the power down state if they are masked in the CPU Available Registers Operand Format and Number of States Require...

Page 182: ...emains unchanged V Previous value remains unchanged C Previous value remains unchanged I UI H U Z V C Description This instruction copies the CCR contents to an 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Register direct STC B CCR Rd 0 2 0 rd 2 No of States Add...

Page 183: ...ious value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged I UI H U N Z V C Description This instruction copies the CCR contents to a destination location Although CCR is a byte register the destination operand is a word operand The CCR contents are stored at the even address Available Registers ERd ER0 to ER7 175 ...

Page 184: ...th byte 9th byte 10th byte Register indirect Register indirect with displacement Register indirect with pre decrement STC W STC W STC W STC W STC W STC W CCR ERd CCR d 16 ERd CCR d 24 ERd CCR ERd CCR aa 16 CCR aa 24 Absolute address 0 0 0 0 0 0 1 1 1 1 1 1 4 4 4 4 4 4 0 0 0 0 0 0 6 6 7 6 6 6 9 F 8 D B B erd erd erd erd 1 1 0 1 0 0 0 0 0 0 6 B A 0 0 disp abs abs 0 0 8 A disp 6 8 12 8 8 10 0 2 2 58 ...

Page 185: ...ontents of an 8 bit register Rd destination operand and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes The SUB B instruction can operate only on general registers Immediate data can be subtracted from general register contents by using the SUBX instruction Before execu...

Page 186: ...ared to 0 C Set to 1 if there is a borrow at bit 15 otherwise cleared to 0 I UI H U N Z V C Description This instruction subtracts a source operand from the contents of a 16 bit register Rd destination operand and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction For...

Page 187: ...o 0 C Set to 1 if there is a borrow at bit 31 otherwise cleared to 0 I UI H U N Z V C Description This instruction subtracts a source operand from the contents of a 32 bit register ERd destination operand and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd...

Page 188: ...ains unchanged I UI H U N Z V C Description This instruction subtracts the immediate value 1 2 or 4 from the contents of a 32 bit register ERd destination register Differing from the SUB instruction it does not affect the condition code flags Available Registers ERd ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte Re...

Page 189: ...therwise cleared to 0 C Set to 1 if there is a borrow from bit 7 otherwise cleared to 0 I UI H U N Z V C Description This instruction subtracts the source operand and carry flag from the contents of an 8 bit register Rd destination operand and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Ins...

Page 190: ...ector address corresponding to the specified vector number The PC value pushed on the stack is the starting address of the next instruction after the TRAPA instruction Operand Format and Number of States Required for Execution Notes 1 CCR bit 6 is set to 1 when used as an interrupt mask bit but retains its previous value when used as a user bit 2 The stack and vector structure differ between norma...

Page 191: ...us value remains unchanged I UI H U N Z V C 0 Description This instruction exclusively ORs the source operand with the contents of an 8 bit register Rd destination register and stores the result in the 8 bit register Rd Available Registers Rd R0L to R7L R0H to R7H Rs R0L to R7L R0H to R7H Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte...

Page 192: ...ous value remains unchanged I UI H U N Z V C 0 Description This instruction exclusively ORs the source operand with the contents of a 16 bit register Rd destination register and stores the result in the 16 bit register Rd Available Registers Rd R0 to R7 E0 to E7 Rs R0 to R7 E0 to E7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th b...

Page 193: ...emains unchanged I UI H U N Z V C 0 Description This instruction exclusively ORs the source operand with the contents of a 32 bit register ERd destination register and stores the result in the 32 bit register ERd Available Registers ERd ER0 to ER7 ERs ER0 to ER7 Operand Format and Number of States Required for Execution Notes Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte...

Page 194: ...he corresponding bit of the result V Stores the corresponding bit of the result C Stores the corresponding bit of the result I UI H U N Z V C Description This instruction exclusively ORs the contents of the condition code register CCR with immediate data and stores the result in the condition code register No interrupt requests including NMI are accepted immediately after execution of this instruc...

Page 195: ...16 aa 24 d 8 PC d 16 PC aa 8 MOV BWL BWL BWL BWL BWL BWL B BWL BWL POP PUSH WL MOVEPE B MOVTPE ADD CMP BWL BWL SUB WL BWL ADDX B B SUBX ADDS L SUBS INC DEC BWL DAA DAS B MULXU BW DIVXU MULXS DIVXS NEG BWL EXTU WL EXTS AND OR BWL BWL XOR NOT BWL Shift operations BWL Bit manipulation B B B Data transfer Arithmetic operations Logic operations 187 ...

Page 196: ...ion Instruction xx Rn ERn d 16 ERn d 24 ERn ERn ERn aa 8 aa 16 aa 24 d 8 PC d 16 PC aa 8 Branch Bcc BSR JMP JSR RTS TRAPA RTE SLEEP LDC B B W W W W W W STC B W W W W W W ANDC B ORC XORC NOP B Legend B Byte W Word L Longword System control Block data transfer 188 ...

Page 197: ... 24 ERd B 8 Rd8 d 24 ERd 0 10 10 MOV B Rs ERd B 2 ERd32 1 ERd32 Rs8 ERd 0 6 6 MOV B Rs aa 8 B 2 Rs8 aa 8 0 4 4 MOV B Rs aa 16 B 4 Rs8 aa 16 0 6 6 MOV B Rs aa 24 B 6 Rs8 aa 24 0 8 8 MOV W xx 16 Rd W 4 xx 16 Rd16 0 4 4 MOV W Rs Rd W 2 Rs16 Rd16 0 2 2 MOV W ERs Rd W 2 ERs24 Rd16 0 4 4 MOV W d 16 ERs Rd W 4 d 16 ERs Rd16 0 6 6 MOV W d 24 ERs Rd W 8 d 24 ERs Rd16 0 10 10 MOV W ERs Rd W 2 ERs Rd16 ERs32...

Page 198: ...6 0 10 10 MOV L ERs aa 24 L 8 ERs32 aa 24 0 12 12 POP POP W Rn W 2 SP Rn16 SP 2 SP 0 6 6 POP L ERn L 4 SP ERn32 SP 4 SP 0 8 10 PUSH PUSH W Rn W 2 SP 2 SP Rn16 SP 0 6 6 PUSH L ERn L 4 SP 4 SP ERn32 SP 0 8 10 MOVFPE MOVFPE aa 16 Rd B 4 aa 16 Rd synchronized with 0 6 6 E clock MOVTPE MOVTPE Rs aa 16 B 4 Rs aa 16 synchronized with 0 6 6 E clock R 2 Arithmetic Operation Instructions Addressing Mode and...

Page 199: ...d8 decimal adjust Rd8 2 2 SUB SUB B Rs Rd B 2 Rd8 Rs8 Rd8 2 2 SUB W xx 16 Rd W 4 Rd16 xx 16 Rd16 1 4 4 SUB W Rs Rd W 2 Rd16 Rs16 Rd16 1 2 2 SUB L xx 32 ERd L 6 ERd32 xx 32 ERd32 2 6 6 SUB L ERs ERd L 2 ERd32 ERs32 ERd32 2 2 2 SUBX SUBX B xx 8 Rd B 2 Rd8 xx 8 C Rd8 3 2 2 SUBX B Rs Rd B 2 Rd8 Rs8 C Rd8 3 2 2 SUBS SUBS L 1 ERd L 2 Erd32 1 ERd32 2 2 SUBS L 2 ERd L 2 ERd32 2 ERd32 2 2 SUBS L 4 ERd L 2 ...

Page 200: ...2 22 22 unsigned operation MULXS MULXS B Rs Rd B 4 Rd8 Rs8 Rd16 16 16 signed operation MULXS W Rs ERd W 4 Rd16 Rs16 ERd32 24 24 signed operation DIVXU DIVXU B Rs Rd B 2 Rd16 Rs8 Rd16 RdH remainder 6 7 14 14 RdL quotient unsigned operation DIVXU W Rs ERd W 2 ERd32 Rs16 ERd32 Ed remainder 6 7 22 22 Rd quotient unsigned operation DIVXS DIVXS B Rs Rd B 4 Rd16 Rs8 Rd16 RdH remainder 8 7 16 16 RdL quoti...

Page 201: ...0 6 6 AND L ERs ERd L 4 ERd32 Λ ERs32 ERd32 0 4 4 OR OR B xx 8 Rd B 2 Rd8 V xx 8 Rd8 0 2 2 OR B Rs Rd B 2 Rd8 V Rs8 Rd8 0 2 2 OR W xx 16 Rd W 4 Rd16 V xx 16 Rd16 0 4 4 OR W Rs Rd W 2 Rd16 V Rs16 Rd16 0 2 2 OR L xx 32 ERd L 6 ERd32 V xx 32 ERd32 0 6 6 OR L ERs ERd L 4 ERd32 V ERs32 ERd32 0 4 4 XOR XOR B xx 8 Rd B 2 Rd8 xx 8 Rd8 0 2 2 XOR B Rs Rd B 2 Rd8 Rs8 Rd8 0 2 2 XOR W xx 16 Rd W 4 Rd16 xx 16 R...

Page 202: ... 2 SHAR L ERd L 2 0 2 2 SHLL SHLL B Rd B 2 0 2 2 SHLL W Rd W 2 0 2 2 SHLL L ERd L 2 0 2 2 SHLR SHLR B Rd B 2 0 2 2 SHLR W Rd W 2 0 2 2 SHLR L ERd L 2 0 2 2 ROTXL ROTXL B Rd B 2 0 2 2 ROTXL W Rd W 2 0 2 2 ROTXL L ERd L 2 0 2 2 ROTXR ROTXR B Rd B 2 0 2 2 ROTXR W Rd W 2 0 2 2 ROTXR L ERd L 2 0 2 2 ROTL ROTL B Rd B 2 0 2 2 ROTL W Rd W 2 0 2 2 ROTL L ERd L 2 0 2 2 ROTR ROTR B Rd B 2 0 2 2 ROTR W Rd W 2...

Page 203: ... BCLR Rn ERd B 4 Rn8 of ERd 0 8 8 BCLR Rn aa 8 B 4 Rn8 of aa 8 0 8 8 BNOT BNOT xx 3 Rd B 2 xx 3 of Rd8 xx 3 of Rd8 2 2 BNOT xx 3 ERd B 4 xx 3 of ERd xx 3 of 8 8 ERd BNOT xx 3 aa 8 B 4 xx 3 of aa 8 xx 3 of aa 8 8 8 BNOT Rn Rd B 2 Rn8 of Rd8 Rn8 of Rd8 2 2 BNOT Rn ERd B 4 Rn8 of ERd Rn8 of ERd 8 8 BNOT Rn aa 8 B 4 Rn8 of aa 8 Rn8 of aa 8 8 8 BTST BTST xx 3 Rd B 2 xx 3 of Rd8 Z 2 2 BTST xx 3 ERd B 4 ...

Page 204: ... ERd B 4 CΛ xx 3 of ERd24 C 6 6 BAND xx 3 aa 8 B 4 CΛ xx 3 of aa 8 C 6 6 BIAND BIAND xx 3 Rd B 2 CΛ xx 3 of Rd8 C 2 2 BIAND xx 3 ERd B 4 CΛ xx 3 of ERd24 C 6 6 BIAND xx 3 aa 8 B 4 CΛ xx 3 of aa 8 C 6 6 BOR BOR xx 3 Rd B 2 C V xx 3 of Rd8 C 2 2 BOR xx 3 ERd B 4 C V xx 3 of ERd24 C 6 6 BOR xx 3 aa 8 B 4 C V xx 3 of aa 8 C 6 6 BIOR BIOR xx 3 Rd B 2 C V xx 3 of Rd8 C 2 2 BIOR xx 3 ERd B 4 C V xx 3 of ...

Page 205: ...BLS d 8 2 C V Z 1 4 BLS d 16 4 6 BCC d 8 BHS d 8 2 C 0 4 BCC d 16 BHS d 16 4 6 BCS d 8 BLO d 8 2 C 1 4 BCS d 16 BLO d 16 4 6 BNE d 8 2 Z 0 4 BNE d 16 4 6 BEQ d 8 2 Z 1 4 BEQ d 16 4 6 BVC d 8 2 V 0 4 BVC d 16 4 6 BVS d 8 2 V 1 4 BVS d 16 4 6 BPL d 8 2 N 0 4 BPL d 16 4 6 BMI d 8 2 N 1 4 BMI d 16 4 6 BGE d 8 2 N V 0 4 BGE d 16 4 6 BLT d 8 2 N V 1 4 BLT d 16 4 6 BGT d 8 2 Z V N V 0 4 BGT d 16 4 6 BLE ...

Page 206: ...ed TRAPA TRAPA x 2 2 PC SP CCR SP 1 14 14 vector PC RTE RTE CCR SP PC SP 10 10 SLEEP SLEEP Transition to power down state 2 2 LDC LDC xx 8 CCR B 2 xx 8 CCR 2 2 LDC Rs CCR B 2 Rs8 CCR 2 2 LDC ERs CCR W 4 ERs CCR 6 6 LDC d 16 ERs CCR W 6 d 16 ERs CCR 8 8 LDC d 16 ERs CCR W 10 d 24 ERs CCR 12 12 LDC ERs CCR W 4 ERs CCR ERs32 2 ERs32 8 8 LDC aa 16 CCR W 6 aa 16 CCR 8 8 LDC aa 24 CCR W 8 aa 24 CCR 10 1...

Page 207: ...p memory For other cases see section 2 6 Number of States Required for Execution 2 n is the value set in register R4L or R4 1 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 2 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 3 Retains its previous value when the result is zero otherwise cleared to 0 4 Set to 1 when the adjustment produces a carry othe...

Page 208: ...IMM ADDX Rs Rd B 0 E rs rd AND AND B xx 8 Rd B E rd IMM AND B Rs Rd B 1 6 rs rd AND W xx 16 Rd W 7 9 6 rd IMM AND W Rs Rd W 6 6 rs rd AND L xx 32 ERd L 7 A 6 0 erd IMM AND L ERs ERd L 0 1 F 0 6 6 0 ers 0 erd ANDC ANDC xx 8 CCR B 0 6 IMM BAND BAND xx 3 Rd B 7 6 0 IMM rd BAND xx 3 ERd B 7 C 0 erd 0 7 6 0 IMM 0 BAND xx 3 aa 8 B 7 E abs 7 6 0 IMM 0 Bcc BRA d 8 BT d 8 4 0 disp BRA d 16 BT d 16 5 8 0 0 ...

Page 209: ... disp BGE d 8 4 C disp BGE d 16 5 8 C 0 disp BLT d 8 4 D disp BLT d 16 5 8 D 0 disp BGT d 8 4 E disp BGT d 16 5 8 E 0 disp BLE d 8 4 F disp BLE d 16 5 8 F 0 disp BCLR BCLR xx 3 Rd B 7 2 0 IMM rd BCLR xx 3 ERd B 7 D 0 erd 0 7 2 0 IMM 0 BCLR xx 3 aa 8 B 7 F abs 7 2 0 IMM 0 BCLR Rn Rd B 6 2 rn rd BCLR Rn ERd B 7 D 0 erd 0 6 2 rn 0 BCLR Rn aa 8 B 7 F abs 6 2 rn 0 BIAND BIAND xx 3 Rd B 7 6 1 IMM rd BIA...

Page 210: ...erd 0 7 7 0 IMM 0 BLD xx 3 aa 8 B 7 E abs 7 7 0 IMM 0 BNOT BNOT xx 3 Rd B 7 1 0 IMM rd BNOT xx 3 ERd B 7 D 0 erd 0 7 1 0 IMM 0 BNOT xx 3 aa 8 B 7 F abs 7 1 0 IMM 0 BNOT Rn Rd B 6 1 rn rd BNOT Rn ERd B 7 D 0 erd 0 6 1 rn 0 BNOT Rn aa 8 B 7 F abs 6 1 rn 0 BOR BOR xx 3 Rd B 7 4 0 IMM rd BOR xx 3 ERd B 7 C 0 erd 0 7 4 0 IMM 0 BOR xx 3 aa 8 B 7 E abs 7 4 0 IMM 0 BSET BSET xx 3 Rd B 7 0 0 IMM rd BSET xx...

Page 211: ...Rs Rd B 1 C rs rd CMP W xx 16 Rd W 7 9 2 rd IMM CMP W Rs Rd W 1 D rs rd CMP L xx 32 ERd L 7 A 2 0 erd IMM CMP L ERs ERd L 1 F 1 ers 0 erd DAA DAA Rd B 0 F 0 rd DAS DAS Rd B 1 F 0 rd DEC DEC B Rd B 1 A 0 rd DEC W 1 Rd W 1 B 5 rd DEC W 2 Rd W 1 B D rd DEC L 1 ERd L 1 B 7 0 erd DEC L 2 ERd L 1 B F 0 erd DIVXS DIVXS B Rs Rd B 0 1 D 0 5 1 rs rd DIVXS W Rs ERd W 0 1 D 0 5 3 rs 0 erd DIVXU DIVXU B Rs Rd ...

Page 212: ... 1 4 0 6 D 0 ers 0 LDC aa 16 CCR W 0 1 4 0 6 B 0 0 abs LDC aa 24 CCR W 0 1 4 0 6 B 2 0 0 0 abs MOV MOV B xx 8 Rd B F rd IMM MOV B Rs Rd B 0 C rs rd MOV B ERs Rd B 6 8 0 ers rd MOV B d 16 ERs Rd B 6 E 0 ers rd disp MOV B d 24 ERs Rd B 7 8 0 ers 0 6 A 2 rd 0 0 disp MOV B ERs Rd B 6 C 0 ers rd MOV B aa 8 Rd B 2 rd abs MOV B aa 16 Rd B 6 A 0 rd abs MOV B aa 24 Rd B 6 A 2 rd 0 0 abs MOV B Rs ERd B 6 8 ...

Page 213: ...MOV L d 16 ERs ERd L 0 1 0 0 6 F 0 ers 0 erd disp MOV L d 24 ERs ERd L 0 1 0 0 7 8 0 ers 0 6 B 2 0 erd 0 0 disp MOV L ERs ERd L 0 1 0 0 6 D 0 ers 0 erd MOV L aa 16 ERd L 0 1 0 0 6 B 0 0 erd abs MOV L aa 24 ERd L 0 1 0 0 6 B 2 0 erd 0 0 abs MOV L ERs ERd L 0 1 0 0 6 9 1 erd 0 ers MOV L ERs d 16 ERd L 0 1 0 0 6 F 1 erd 0 ers disp MOV L ERs d 24 ERd L 0 1 0 0 7 8 0 erd 0 6 B A 0 ers 0 0 disp MOV L ER...

Page 214: ...MM POP POP W Rn W 6 D 7 rn POP L ERn L 0 1 0 0 6 D 7 0 ern PUSH PUSH W Rn W 6 D F rn PUSH L ERn L 0 1 0 0 6 D F 0 ern ROTL ROTL B Rd B 1 2 8 rd ROTL W Rd W 1 2 9 rd ROTL L ERd L 1 2 B 0 erd ROTR ROTR B Rd B 1 3 8 rd ROTR W Rd W 1 3 9 rd ROTR L ERd L 1 3 B 0 erd ROTXL ROTXL B Rd B 1 2 0 rd ROTXL W Rd W 1 2 1 rd ROTXL L ERd L 1 2 3 0 erd ROTXR ROTXR B Rd B 1 3 0 rd ROTXR W Rd W 1 3 1 rd ROTXR L ERd ...

Page 215: ...0 0 disp STC CCR ERd W 0 1 4 0 6 D 1 erd 0 STC CCR aa 16 W 0 1 4 0 6 B 8 0 abs STC CCR aa 24R W 0 1 4 0 6 B A 0 0 0 abs SUB SUB B Rs Rd B 1 8 rs rd SUB W xx 16 Rd W 7 9 3 rd IMM SUB W Rs Rd W 1 9 rs rd SUB L xx 32 ERd L 7 A 3 0 erd IMM SUB L ERs ERd L 1 A 1 ers 0 erd SUBS SUBS 1 ERd L 1 B 0 0 erd SUBS 2 ERd L 1 B 8 0 erd SUBS 4 ERd L 1 B 9 0 erd SUBX SUBX xx 8 Rd B B rd IMM SUBX Rs Rd B 1 E rs rd ...

Page 216: ...egister field 3 bits specifying a 32 bit register ers corresponds to operand symbols such as ERs erd corresponds to operand symbols such as ERd and ern corresponds to the operand symbol ERn The register fields specify general registers as follows Address Register 32 bit Register 16 bit Register 8 bit Register Register General Register General Register General Field Register Field Register Field Re...

Page 217: ...BSR XOR W 6 ANDC AND B BNE RTE AND W 7 LDC Table 2 5 BEQ TRAPA 8 SUB B BVC Table 2 5 MOV 9 SUB W BVS Table 2 5 A Table 2 5 Table 2 5 BPL JMP Table 2 5 B Table 2 5 Table 2 5 BMI EEPMOV C MOV CMP BGE BSR MOV D BLT E ADDX SUBX BGT JSR F Table 2 5 Table 2 5 BLE BOR BIOR BXOR BIXOR BAND BIAND BST BIST BLD BILD Table 2 6 ADD ADDX CMP SUBX OR XOR AND MOV Operation Code 1st byte 2nd byte AH AL BH BL Instr...

Page 218: ...UBS DAS BRA MOV MOV 1 BRN ADD ADD 2 BHI CMP CMP 3 SHLL SHLR ROTXL ROTXR NOT BLS SUB SUB 4 BCC OR OR 5 INC EXTU DEC BCS XOR XOR 6 BNE AND AND 7 INC EXTU DEC BEQ 8 SLEEP ADDS BVC A BPL B SHAL SHAR ROTL ROTR NEG BMI C Table 2 6 BGE D Table 2 6 INC EXTS DEC BLT E BGT F Table 2 6 INC EXTS DEC BLE ADD MOV SUB CMP SHLL SHLR ROTXL ROTXR NOT LDC STC SHAL SHAR ROTL ROTR NEG SUB ...

Page 219: ...BSET BSET BSET 1 DIVXS BNOT BNOT BNOT BNOT 2 MULXS BCLR BCLR BCLR BCLR 3 DIVXS BTST BTST BTST BTST 4 OR 5 XOR 6 AND 7 8 9 A B C D E F BOR BIOR BXOR BIXOR BAND BIAND BID BILD BST BIST BOR BIOR BXOR BIXOR BAND BIAND BID BILD BST BIST r is a register field aa is an absolute address field Instruction when most significant bit of DH is 0 Instruction when most significant bit of DH is 1 Notes 1 2 1 1 1 ...

Page 220: ...required for execution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SK M SM N SN Examples Advanced mode stack located in external memory on chip supporting modules accessed with 8 bit bus width external devices accessed in three states with one wait state and 16 bit bus width 1 BSET 0 FFFFC7 8 From table 2 8 I L 2 J K M N 0 From table 2 7 S...

Page 221: ... Access Access Access Instruction fetch SI 2 6 3 4 6 2 m 2 3 m Branch address read SJ Stack operation SK Byte data access SL 3 2 3 m Word data access SM 6 4 6 2 m Internal operation SN 1 1 1 1 1 1 1 Note For the MOVFPE and MOVTPE instructions refer to the relevant microcontroller hardware manual Legend m Number of wait states inserted into external device access External Device 213 ...

Page 222: ... 4 ERd 1 ADDX ADDX xx 8 Rd 1 ADDX Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 AND W xx 16 Rd 2 AND W Rs Rd 1 AND L xx 32 ERd 3 AND L ERs ERd 2 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 ERd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8...

Page 223: ... 16 2 2 BCLR BCLR xx 3 Rd 1 BCLR xx 3 ERd 2 2 BCLR xx 3 aa 8 2 2 BCLR Rn Rd 1 BCLR Rn ERd 2 2 BCLR Rn aa 8 2 2 BIAND BIAND xx 3 Rd 1 BIAND xx 3 ERd 2 1 BIAND xx 3 aa 8 2 1 BILD BILD xx 3 Rd 1 BILD xx 3 ERd 2 1 BILD xx 3 aa 8 2 1 BIOR BIOR xx 8 Rd 1 BIOR xx 8 ERd 2 1 BIOR xx 8 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 ERd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 ERd 2 1 BIXOR xx 3 aa 8 ...

Page 224: ... 1 BSET Rn ERd 2 2 BSET Rn aa 8 2 2 BSR BSR d 8 Advanced 2 2 Normal 2 1 BSR d 16 Advanced 2 2 2 Normal 2 1 2 BST BST xx 3 Rd 1 BST xx 3 ERd 2 2 BST xx 3 aa 8 2 2 BTST BTST xx 3 Rd 1 BTST xx 3 ERd 2 1 BTST xx 3 aa 8 2 1 BTST Rn Rd 1 BTST Rn ERd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 ERd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W xx 16 Rd 2 CMP W Rs Rd 1 CMP L xx 32 E...

Page 225: ...NC W 1 2 Rd 1 INC L 1 2 ERd 1 JMP JMP ERn 2 JMP aa 24 2 2 JMP aa 8 Advanced 2 2 2 Normal 2 1 2 JSR JSR ERn Advanced 2 2 Normal 2 1 JSR aa 24 Advanced 2 2 2 Normal 2 1 2 JSR aa 8 Advanced 2 2 2 Normal 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 LDC ERs CCR 2 1 LDC d 16 ERs CCR 3 1 LDC d 24 ERs CCR 5 1 LDC ERs CCR 2 1 2 LDC aa 16 CCR 3 1 LDC aa 24 CCR 4 1 MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B ERs Rd 1 1...

Page 226: ...s Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W aa 24 Rd 3 1 MOV W Rs ERd 1 1 MOV W Rs d 16 ERd 2 1 MOV W Rs d 24 ERd 4 1 MOV W Rs ERd 1 1 2 MOV W Rs aa 16 2 1 MOV W Rs aa 24 3 1 MOV L xx 32 ERd 3 MOV L ERs ERd 1 MOV L ERs ERd 2 2 MOV L d 16 ERs ERd 3 2 MOV L d 24 ERs ERd 5 2 MOV L ERs ERd 2 2 2 MOV L aa 16 ERd 3 2 MOV L aa 24 ERd 4 2 MOV L ERs ERd 2 2 MOV L ERs d 16 ERd 3 2 MOV L ERs d 24 ERd 5 2 MOV L ERs E...

Page 227: ...B xx 8 Rd 1 OR B Rs Rd 1 OR W xx 16 Rd 2 OR W Rs Rd 1 OR L xx 32 ERd 3 OR L ERs ERd 2 ORC ORC xx 8 CCR 1 POP POP W Rn 1 1 2 POP L ERn 2 2 2 PUSH PUSH W Rn 1 1 2 PUSH L ERn 1 2 2 ROTL ROTL B Rd 1 ROTL W Rd 1 ROTL L ERd 1 ROTR ROTR B Rd 1 ROTR W Rd 1 ROTR L ERd 1 ROTXL ROTXL B Rd 1 ROTXL W Rd 1 ROTXL L ERd 1 ROTXR ROTXR B Rd 1 ROTXR W Rd 1 ROTXR L ERd 1 RTE RTE 2 2 2 RTS RTS Advanced 2 2 2 Normal 2 ...

Page 228: ...1 SHLR L ERd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 STC CCR ERd 2 1 STC CCR d 16 ERd 3 1 STC CCR d 24 ERd 5 1 STC CCR ERd 2 1 2 STC CCR aa 16 3 1 STC CCR aa 24 4 1 SUB SUB B Rs Rd 1 SUB W xx 16 Rd 2 SUB W Rs Rd 1 SUB L xx 32 ERd 3 SUB L ERs ERd 1 SUBS SUBS 1 2 4 ERd 1 SUBX SUBX xx 8 Rd 1 SUBX Rs Rd 1 TRAPA TRAPA x 2 Advanced 2 2 2 4 Normal 2 1 2 4 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XOR W xx 16 Rd 2 XOR W...

Page 229: ... for byte operands Si The i th bit of the source operand Di The i th bit of the destination operand Ri The i th bit of the result Dn The specified bit in the destination operand Not affected Modified according to the result of the instruction see definition 0 Always cleared to 0 1 Always set to 1 Undetermined no guaranteed value Z Z flag before instruction execution C C flag before instruction exe...

Page 230: ...4 R m 4 N R m Z Z R m R 0 V S m D m R m S m D m R m C S m D m D m R m S m R m AND O N R m Z R m R m 1 R 0 ANDC Stores the corresponding bits of the result BAND C C D n Bcc BCLR BIAND C C D n BILD C D n BIOR C C D n BIST BIXOR C C D n C D n BLD C D n BNOT BOR C C D n BSET BSR BST BTST Z D n BXOR C C D n C D n CMP H S m 4 D m 4 D m 4 R m 4 S m 4 R m 4 N R m Z R m R m 1 R 0 V S m D m R m S m D m R m ...

Page 231: ... m DIVXS N S m D m S m D m Z S m S m 1 S 0 DIVXU N S m Z S m S m 1 S 0 EEPMOV EXTS O N R m Z R m R m 1 R 0 EXTU O O Z R m R m 1 R 0 INC N R m Z R m R m 1 R 0 V D m R m JMP JSR LDC Stores the corresponding bits of the result MOV O N R m Z R m R m 1 R 0 MOVFPE O N R m Z R m R m 1 R 0 MOVTPE O N R m Z R m R m 1 R 0 MULXS N R 2 m Z R 2 m R 2 m 1 R 0 MULXU NEG H D m 4 R m 4 N R m Z R m R m 1 R 0 V D m ...

Page 232: ...lt POP O N R m Z R m R m 1 R 0 PUSH O N R m Z R m R m 1 R 0 ROTL O N R m Z R m R m 1 R 0 C D m ROTR O N R m Z R m R m 1 R 0 C D 0 ROTXL O N R m Z R m R m 1 R 0 C D m ROTXR O N R m Z R m R m 1 R 0 C D 0 RTS RTE Stores the corresponding bits of the result SHAL N R m Z R m R m 1 R 0 V D m D m 1 D m D m 1 C D m SHAR O N R m Z R m R m 1 R 0 C D 0 SHLL O N R m Z R m R m 1 R 0 C D m 224 ...

Page 233: ... SUB H S m 4 D m 4 D m 4 R m 4 S m 4 R m 4 N R m Z R m R m 1 R 0 V S m D m R m S m D m R m C S m D m D m R m S m R m SUBS SUBX H S m 4 D m 4 D m 4 R m 4 S m 4 R m 4 N R m Z Z R m R 0 V S m D m R m S m D m R m C S m D m D m R m S m R m TRAPA XOR O N R m Z R m R m 1 R 0 XORC Stores the corresponding bits of the result 225 ...

Page 234: ...e W W Word size write 2nd Address of 2nd word 3rd and 4th bytes 3rd Address of 3rd word 5th and 6th bytes 4th Address of 4th word 7th and 8th bytes 5th Address of 5th word 9th and 10th bytes NEXT Address of next instruction EA Effective address VEC Vector address Internal operation 2 states Order of bus cycles End of instruction Read effective address word size read No read or write Instruction 1 ...

Page 235: ...bus using 3 state access with no wait states Figure 2 1 Address Bus RD and WR HWR or LWR Timing 8 bit bus 3 state access no wait states ø Address bus RD WR HWR or LWR High level Internal operation Fetching 3rd byte of instruction Fetching 4th byte of instruction Fetching 1st byte of jump address Fetching 2nd byte of jump address R W EA R W 2nd 227 ...

Page 236: ...2nd R W NEXT AND W Rs Rd R W NEXT AND L xx 32 ERd R W 2nd R W 3rd R W NEXT AND L ERs ERd R W 2nd R W NEXT ANDC xx 8 CCR R W NEXT BAND xx 3 Rd R W NEXT BAND xx 3 ERd R W 2nd R B EA R W NEXT BAND xx 3 aa 8 R W 2nd R B EA R W NEXT BRA d 8 BT d 8 R W NEXT R W EA BRN d 8 BF d 8 R W NEXT R W EA BHI d 8 R W NEXT R W EA BLS d 8 R W NEXT R W EA BCC d 8 BHS d 8 R W NEXT R W EA BCS d 8 BLO d 8 R W NEXT R W E...

Page 237: ...nal operation R W EA 2 states BCS d 16 BLO d 16 R W 2nd Internal operation R W EA 2 states BNE d 16 R W 2nd Internal operation R W EA 2 states BEQ d 16 R W 2nd Internal operation R W EA 2 states BVC d 16 R W 2nd Internal operation R W EA 2 states BVS d 16 R W 2nd Internal operation R W EA 2 states BPL d 16 R W 2nd Internal operation R W EA 2 states BMI d 16 R W 2nd Internal operation R W EA 2 stat...

Page 238: ...2nd R B EA R W NEXT BIST xx 3 Rd R W NEXT BIST xx 3 ERd R W 2nd R B EA R W NEXT W B EA BIST xx 3 aa 8 R W 2nd R B EA R W NEXT W B EA BIXOR xx 3 Rd R W NEXT BIXOR xx 3 ERd R W 2nd R B EA R W NEXT BIXOR xx 3 aa 8 R W 2nd R B EA R W NEXT BLD xx 3 Rd R W NEXT BLD xx 3 ERd R W 2nd R B EA R W NEXT BLD xx 3 aa 8 R W 2nd R B EA R W NEXT BNOT xx 3 Rd R W NEXT BNOT xx 3 ERd R W 2nd R B EA R W NEXT W B EA BN...

Page 239: ...XT BTST Rn aa 8 R W 2nd R B EA R W NEXT BXOR xx 3 Rd R W NEXT BXOR xx 3 ERd R W 2nd R B EA R W NEXT BXOR xx 3 aa 8 R W 2nd R B EA R W NEXT CMP B xx 8 Rd R W NEXT CMP B Rs Rd R W NEXT CMP W xx 16 Rd R W 2nd R W NEXT CMP W Rs Rd R W NEXT CMP L xx 32 ERd R W 2nd R W 3rd R W NEXT CMP L ERs ERd R W NEXT DAA Rd R W NEXT DAS Rd R W NEXT DEC B Rd R W NEXT DEC W 1 2 Rd R W NEXT DEC L 1 2 ERd R W NEXT DIVXS...

Page 240: ...n R W EA W W Stack 2 states Advanced R W 2nd Internal operation R W EA W W Stack H W W Stack L 2 states JSR aa 8 Normal R W NEXT R W aa 8 W W Stack R W EA Advanced R W NEXT R W aa 8 R W aa 8 W W Stack H W W Stack L R W EA LDC xx 8 CCR R W NEXT LDC Rs CCR R W NEXT LDC ERs CCR R W 2nd R W NEXT R W EA LDC d 16 ERs CCR R W 2nd R W 3rd R W NEXT R W EA LDC d 24 ERs CCR R W 2nd R W 3rd R W 4th R W 5th R ...

Page 241: ... ERs Rd R W 2nd R W NEXT R W EA MOV W d 24 ERs Rd R W 2nd R W 3rd R W 4th R W NEXT R W EA MOV W ERs Rd R W NEXT Internal operation R W EA 2 states MOV W aa 16 Rd R W 2nd R W NEXT R W EA MOV W aa 24 Rd R W 2nd R W 3rd R W NEXT R B EA MOV W Rs ERd R W NEXT W W EA MOV W Rs d 16 ERd R W 2nd R W NEXT W W EA MOV W Rs d 24 ERd R W 2nd R W 3rd R E 4th R W NEXT W W EA MOV W Rs ERd R W NEXT Internal operati...

Page 242: ...d R W 2nd Internal operation R W 3 EA 2 states MOVTPE Rs aa 16 R W 2nd Internal operation W B 3 EA 2 states MULXS B Rs Rd R W 2nd R W NEXT Internal operation 12 states MULXS W Rs ERd R W 2nd R W NEXT Internal operation 20 states MULXU B Rs Rd R W NEXT Internal operation 12 states MULXU W Rs ERd R W NEXT Internal operation 20 states NEG B Rd R W NEXT NEG W Rd R W NEXT NEG L ERd R W NEXT NOP R W NEX...

Page 243: ...XL L ERd R W NEXT ROTXR B Rd R W NEXT ROTXR W Rd R W NEXT ROTXR L ERd R W NEXT RTE R W NEXT R W Stack H R W Stack L Internal operation R W 4 2 states RTS Normal R W NEXT R W Stack Internal operation R W 4 2 states Advanced R W NEXT R W Stack H R W Stack L Internal operation R W 4 2 states SHAL B Rd R W NEXT SHAL W Rd R W NEXT SHAL L ERd R W NEXT SHAR B Rd R W NEXT SHAR W Rd R W NEXT SHAR L ERd R W...

Page 244: ...EXT Internal operation W W Stack L W W Stack H R W VEC Internal operation R W 7 2 states 2 states Advanced R W NEXT Internal operation W W Stack L W W Stack H R W VEC R W VEC 2 Internal operation R W 7 2 states 2 states XOR B xx8 Rd R W NEXT XOR B Rs Rd R W NEXT XOR W xx 16 Rd R W 2nd R W NEXT XOR W Rs Rd R W NEXT XOR L xx 32 ERd R W 2nd R W 3rd R W NEXT XOR L ERs ERd R W 2nd R W NEXT XORC xx 8 CC...

Page 245: ...arting address of the program 6 Prefetch address equal to two plus the PC value pushed on the stack In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation 7 Starting address of the interrupt handling routine 8 NEXT Next address after the current instruction 2nd Address of the second word of the current instruction 3rd Address of the third word ...

Page 246: ...ng States Program execution state The CPU executes program instructions in sequence Exception handling state A transient state in which the CPU executes a hardware sequence saving the program counter and condition code register fetching a vector etc in response to a reset interrupt or other exception Bus released state The external bus has been released in response to an external or internal bus r...

Page 247: ...Sleep mode Exception handling state External interrupt Software standby mode RES high Bus request completion Bus request Reset state STBY high RES low Hardware standby mode Power down state S L E E P i n s t r u c t i o n w i t h S S B Y 1 S L E E P i n s t r u c t i o n w i t h S S B Y 0 1 Notes 1 From any state except hardware standby mode a transition to the reset state occurs whenever RES goes...

Page 248: ...ty Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with Exception handling starts clock immediately when RES changes from low to high Interrupt End of instruction When an interrupt is requested execution see note exception handling starts at the end of the current instruction or current exception handling sequence Trap instruction When TRAPA Exception handlin...

Page 249: ... it ends Interrupt Exception Handling and Trap Instruction Exception Handling When these exception handling sequences begin the CPU references the stack pointer ER7 and pushes the program counter and condition code register on the stack Next if the UE bit in the system control register SYSCR is set to 1 the CPU sets the I bit in the condition code register to 1 If the UE bit is cleared to 0 the CP...

Page 250: ... handling ends b Stack structure in advanced mode Pushed on stack Pushed on stack Legend Program counter PC bits 23 to 16 Program counter PC bits 15 to 8 Program counter PC bits 7 to 0 Condition code register Stack pointer PCE PCH PCL CCR SP Ignored at return 1 PC is the address of the first instruction executed after the return from the exception handling routine 2 Registers must be saved and res...

Page 251: ...e For details refer to the relevant microcontroller hardware manual 3 6 1 Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit SSBY is cleared to 0 CPU operations stop immediately after execution of the SLEEP instruction The contents of CPU registers are retained 3 6 2 Software Standby Mode A transition to software standby mode is made i...

Page 252: ...evant microcontroller hardware manual for details 4 2 On Chip Memory RAM ROM For high speed processing on chip memory is accessed in two states The data bus is 16 bits wide permitting both byte and word access Figure 4 1 shows the on chip memory access cycle Figure 4 2 shows the pin states Figure 4 1 On Chip Memory Access Cycle Internal address bus Internal read signal Internal data bus read acces...

Page 253: ...Figure 4 2 Pin States during On Chip Memory Access Bus cycle T1 state T2 state Address Address bus AS High RD High WR HWR or LWR High Data bus high impedance state ø 246 ...

Page 254: ... 3 shows the access timing for the on chip supporting modules Figure 4 4 shows the pin states Figure 4 3 On Chip Supporting Module Access Cycle Bus cycle T1 state T2 state Address Read data Write data T3 state Internal address bus Internal read signal Internal data bus read access Internal write signal Internal data bus write access ø 247 ...

Page 255: ...ng for two state or three state access Figure 4 6 shows the write timing for two state or three state access In three state access wait states can be inserted by the wait state controller or other means For further details refer to the relevant microcontroller hardware manual Bus cycle T1 state T2 state Address Address bus AS High RD High WR HWR or LWR High Data bus high impedance state ø T3 state...

Page 256: ...Access Timing 1 Read Timing Read cycle T1 state T2 state Address Read data two state access Address bus AS RD Data bus ø Read cycle T1 state T2 state Address Read data three state access T3 state Address bus AS RD Data bus ø 249 ...

Page 257: ... Write Timing Write cycle T1 state T2 state Address a Two state access Address bus AS WR HWR or LWR Data bus ø Write data Write cycle T1 state T2 state Address Write data b Three state access T3 state Address bus AS WR HWR or LWR Data bus ø 250 ...

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