
2.2.56 (1) SHLR (B)
SHLR (SHift Logical Right)
Shift Logical
Operation
Rd (right logical shift)
→
Rd
Assembly-Language Format
SHLR.B
Rd
Operand Size
Byte
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z:
Set to 1 if the result is zero; otherwise
cleared to 0.
V: Always cleared to 0.
C: Receives the previous value in bit 0.
I
UI
H
U
N
Z
V
C
—
—
—
—
0
↕
0
↕
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. The
least significant bit shifts into the carry flag. The most significant bit (bit 7) is cleared to 0.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
LSB
MSB
b
7
b
0
. . . . . .
0
C
Instruction Format
1st byte
2nd byte
3rd byte
4th byte
Register direct
SHLR.B
Rd
1
1
0
rd
2
No. of
States
Addressing
Mode
Mnemonic
Operands
170