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9

Appendix C

P1 and P2 Connector Pin Assignations

P1 CONNECTOR PIN ASSIGNMENTS

PIN

SIGNAL

PIN

SIGNAL

PIN

SIGNAL

A1

N/C

B1

+5V

C1

GND

A2

N/C

B2

GND

C2

N/C

A3

N/C

B3

N/C

C3

N/C

A4

N/C

B4

N/C

C4

N/C

A5

QI0

B5

N/C

C5

QI1

A6

GND

B6

N/C

C6

QI2

A7

QI3

B7

N/C

C7

QI4

A8

QI5

B8

N/C

C8

QI6

A9

QI7

B9

N/C

C9

QI8

A10

QI9

B10

N/C

C10

GND

A11

N/C

B11

N/C

C11

N/C

A12

N/C

B12

GND

C12

N/C

A13

N/C

B13

+5V

C13

N/C

A14

N/C

B14

N/C

C14

II0

A15

II1

B15

N/C

C15

GND

A16

II2

B16

N/C

C16

II3

A17

II4

B17

N/C

C17

II5

A18

II6

B18

N/C

C18

II7

A19

II8

B19

N/C

C19

II9

A20

GND

B20

N/C

C20

CLKIN

A21

GND

B21

N/C

C21

N/C

A22

GND

B22

GND

C22

N/C

A23

GND

B23

N/C

C23

N/C

A24

GND

B24

N/C

C24

N/C

A25

GND

B25

N/C

C25

N/C

A26

N/C

B26

N/C

C26

N/C

A27

N/C

B27

N/C

C27

N/C

A28

N/C

B28

N/C

C28

N/C

A29

N/C

B29

N/C

C29

N/C

A30

N/C

B30

N/C

C30

GND

A31

N/C

B31

GND

C31

N/C

A32

N/C

B32

+5V

C32

N/C

P2 CONNECTOR PIN ASSIGNMENTS

PIN

SIGNAL

PIN

SIGNAL

PIN

SIGNAL

A1

N/C

B1

+5V

C1

GND

A2

N/C

B2

GND

C2

N/C

A3

N/C

B3

N/C

C3

N/C

A4

N/C

B4

N/C

C4

N/C

A5

BO0

B5

N/C

C5

BO1

A6

GND

B6

N/C

C6

BO2

A7

BO3

B7

N/C

C7

BO4

A8

BO5

B8

N/C

C8

BO6

A9

BO7

B9

N/C

C9

BO8

A10

BO9

B10

N/C

C10

GND

A11

N/C

B11

N/C

C11

N/C

A12

N/C

B12

GND

C12

N/C

A13

N/C

B13

+5V

C13

N/C

A14

N/C

B14

N/C

C14

AO0

A15

AO1

B15

N/C

C15

GND

A16

AO2

B16

N/C

C16

AO3

A17

AO4

B17

N/C

C17

AO5

A18

AO6

B18

N/C

C18

AO7

A19

AO8

B19

N/C

C19

AO9

A20

GND

B20

N/C

C20

CLKOUT

A21

GND

B21

N/C

C21

GPOUT

A22

GND

B22

GND

C22

N/C

A23

GND

B23

N/C

C23

N/C

A24

GND

B24

N/C

C24

N/C

A25

GND

B25

N/C

C25

N/C

A26

N/C

B26

N/C

C26

N/C

A27

N/C

B27

N/C

C27

N/C

A28

N/C

B28

N/C

C28

N/C

A29

N/C

B29

N/C

C29

N/C

A30

N/C

B30

N/C

C30

GND

A31

N/C

B31

GND

C31

N/C

A32

N/C

B32

+5V

C32

N/C

HSP50110/210EVAL

Summary of Contents for HSP50210EVAL

Page 1: ...tions of the evaluation circuit board The circuit board is a 3U x 160mm VME Eurocard form factor with dual 96 pin I O connectors The connector pinouts conforms to the VME P2 connector pinout i e power...

Page 2: ...File Exit A typical operational sequence is A Load Configuration File Executing this MAIN MENU item brings up a screen with the current file name and requests the name of the file to be loaded Once th...

Page 3: ...ntroller control signals A microprocessor RESET function can be implemented by installing a normally open push button switch across pins 9 and 10 of JP6 Header JP7 contains the RS232 connection to the...

Page 4: ...any adjustments to the parameters by entering the desired item number and editing it 7 ___ Repeat Steps 5 and 6 for MAIN MENU items 2 3 and 4 These Menus should match the items found in Figures 6 7 a...

Page 5: ...k 0 01 6 Carrier Tracking Loop Damping 0 707 7 AFC Disabled 8 Frequency Error Gain Acq n a Hz Hz 9 Frequency Error Gain Trk n a Hz Hz 10 Delay in Discriminator 0 5 baud 11 Acquisition Sweep Rate 5 Hz...

Page 6: ...d Cosine Filter Several filter coefficient files have been included on the HSP50110 210EVAL disk because the SERINADE program does not compute square root of raised cosine filters These files are prov...

Page 7: ...Three ACT86 gates U3 isolate the on board and off board clock signals allow different polarities for the clocks and provide the 3 0V minimum VIH required by the HSP parts Installing a jumper between...

Page 8: ...TO JP2 1 JP2 2 JP2 3 JP2 4 JP2 5 JP2 6 JP2 7 JP2 8 JP2 9 JP2 10 JP2 29 JP2 30 JP4 1 JP4 2 JP4 3 JP4 4 JP4 5 JP4 6 JP4 7 JP4 8 P1 HSP50110 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 P2 HSP50210 HSP43124...

Page 9: ...N C B28 N C C28 N C A29 N C B29 N C C29 N C A30 N C B30 N C C30 GND A31 N C B31 GND C31 N C A32 N C B32 5V C32 N C P2 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL PIN SIGNAL PIN SIGNAL A1 N C B1 5V C1 GND A2...

Page 10: ...30 GND Ground 31 AGCLVL A D Input to 68HC11 32 GND Ground JP2 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 DQTPH1 DQT Phase Shift Bit1 3 GND Ground 4 DQTPH...

Page 11: ...BB1 Q Baseband 1 26 QBB0 Q Baseband Bit 0 LSB 27 GND Ground 28 GND Ground 29 BBDRDY DCL Input Enable 30 GND Ground 31 AGCLVL A D Input to 68HC11 32 GND Ground JP4 TEST HEADER PIN ASSIGNMENTS PIN SIGNA...

Page 12: ...GND Ground 28 GND Ground 29 DATACLK Output Symbol Clock 30 GND Ground 31 GPOUT Jumper to Pin 29 to Connect DATACLK to P2 32 GND Ground JP6 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNA...

Page 13: ...s Bit 1 25 PA2 6811 Address Bit 2 26 PA3 6811 Address Bit 3 27 PA4 6811 Address Bit 4 28 PA5 6811 Address Bit 5 29 PA6 6811 Address Bit 6 30 PA7 6811 Address Bit 7 31 GND Ground 32 GND Ground 33 PA8 6...

Page 14: ...14 Appendix E Detailed Schematics HSP50110 210EVAL...

Page 15: ...15 HSP50110 210EVAL...

Page 16: ...16 HSP50110 210EVAL...

Page 17: ...17 HSP50110 210EVAL...

Page 18: ...18 HSP50110 210EVAL...

Page 19: ...19 HSP50110 210EVAL...

Page 20: ...20 HSP50110 210EVAL...

Page 21: ...21 HSP50110 210EVAL...

Page 22: ...22 HSP50110 210EVAL...

Page 23: ...23 HSP50110 210EVAL...

Page 24: ...24 HSP50110 210EVAL...

Page 25: ...25 HSP50110 210EVAL...

Page 26: ...6 7 8 3 16 PTC30DAAN Conn 2 x 30 Pin Header SULLINS JP9 1 17 PTC25DAAN Conn 2 x 25 Pin Header SULLINS JP1 5 5 18 510AG91D20ES Socket SIP Socket 20 Pin AUGAT XU4 5 13 6 19 814 AG11D Socket DIP Socket 1...

Page 27: ...R Registers 4208 42FF Unused 248 Bytes 4300 44FF QFIR Coefficients 4500 4507 QFIR Registers 4508 45FF Unused 248 Bytes 4600 467F DCL Registers 00 31d MSB FIRST 4680 46FF Unused 128 Bytes 4700 471F DQT...

Page 28: ...e Generated by DMDEVAL4 EXE Containing Coefficients for the HSP43124 Both Channels PROGRAM EXECUTION FILE DESCRIPTION FILENM Holds File Prefix for Last Configuration Saved Loaded on Start up modified...

Page 29: ...QPSK 3 OQPSK 4 8PSK Item 8 Baud Rate 1 to 56 000 000 Symbols s This is the output symbol rate of the HSP50210 Note that entering a value greater than one half the clock rate induces excessive aliasing...

Page 30: ...ate for the AGC in the HSP50210 This AGC adjusts for changes in signal level due to SNR changes or signals coming and going inside the filter band of the HSP50110 This AGC is typically set to slew slo...

Page 31: ...elay chosen The delay can be set to 1 2 4 8 or 16 samples 0 5 1 2 4 or 8 baud intervals Item 11 Acquisition Sweep Rate 0Hz baud to 1 000 000Hz baud This is the amount that the lag accumulator is incre...

Page 32: ...clock The master clock slower clock selection is done here and the speed of the slower clock slow clock is selected in menu item 14 of the carrier loop menu If the tracking is done via the HSP50110 t...

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