Harris HSP50210EVAL, User Manual

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3
D. Generate Output Files
This command will generate a number of intermediate files
which contain the register values for the IC’s on the evaluation
circuit board. Four of the files, IFIRCOEF.ARY, IFIRREG.ARY,
QFIRCOEF.ARY and QFIRREG.ARY, contain FIR specific con-
figuration and coefficient data. One additional file has a suffix of
.ARY, and the prefix of the last saved configuration filename. It
contains the configuration data for the Digital Tuner and Digital
PLL chips.
E. Configure Hardware
This command accesses a menu called the HARDWARE
INTERFACE MENU. The menu allows selection of full initial-
ization, loading of only the HSP50110 and HSP50210 IC’s,
loading of only the FIR filters, or changing only one specific
register. Full initialization should be selected the first time the
evaluation board is configured. Selection of items 1 - 5 will
create a number of .S files that transfer the configuration
data to the microcontroller on the evaluation circuit board
and call microcontroller subroutines that load the data into
the IC’s on the evaluation board.
D. Display Status
This command in the HARDWARE INTERFACE MENU config-
ures the PC screen to display a variety of status information.
Should further adjustment in the configuration be required, a
partial hardware download can be done using the same pro-
cess and using a command item other than Full Initialization
in the Hardware Interface menu.
For a detailed listing of the every Menu screen, with selec-
tion item definitions, refer to Appendix I.
Configuration/Test Headers
Ten dual row test headers located on the evaluation circuit
board are used to monitor signals and set control pins. The
pin assignments for each of these headers are found in
Appendix D. Headers JP1, 3, and 5 contain the data path sig-
nals for monitoring the input and output busses of the
HSP50110 and HSP50210. Input pins for the HSP50110 have
pull down resistors. Headers JP2 and JP4 contain the I/O sig-
nals for the HSP50110/210 that are not in the data path. JP2
also selects the clock source for the board. Header JP6 con-
tains the microcontroller control signals. A microprocessor
RESET function can be implemented by installing a “normally
open” push button switch across pins 9 and 10 of JP6. Header
JP7 contains the RS232 connection to the 68HC11 microcon-
troller. Header JP8 contains the HSP50210 output I data at
RS232 levels. Header JP9 allows monitoring of the microcon-
troller busses. JP10 co5VDC and ground.
Typical Evaluation Configuration
Figure 3 identifies the equipment configuration in a typical
performance evaluation setup. A test data stream is gener-
ated in the Bit Error Rate Tester (BERT) and used by the
modulator to generate a modulated IF signal. Noise and
other signal impairments are summed with the IF signal, fil-
tered, then digitized by an A/D converter. The digitized IF
signal is routed to the circuit board. From the evaluation
board, recovered clock and data are returned to the BERT
for calculation of BER performance. A computer is con-
nected via RS232 for control and status of the circuit board.
A logic analyzer is shown for viewing real time display of the
I/Q constellations, filter outputs, or error detector outputs of
the HSP50210 during operation.
Getting Started
Evaluation Circuit Board Configuration and Set Up
1. ___ Connect the serial cable, provided in the evaluation kit,
to JP7 on the evaluation board.
2. ___ Connect the DB-9 end of the serial cable to the COM
port on the PC.
3. ___ C5 VDC to the evaluation board at J1, using
the cable provided in the kit. The lead with the white
stripe is the +5 VDC wire. (The board draws approxi-
mately 400mA when operated with the on board
40MHz oscillator)
4. ___ Verify that JP2 has pin 29 jumpered to pin 30, as well
as pin 31 jumpered to pin 32. Installing these jumpers
utilizes the on board 40MHz oscillator. (Set the jump-
ers on JP2, to connect pin 29 to 30, if the on board
oscillator is not desired. Supply an external clock
source on pins 3 and 4 of JP1.)
The circuit board is ready for use when the +5 VDC is
applied to it.
Σ
ADJ. CHANNEL
NOISE SOURCE
MODULATOR
DATA AND CLOCK
MODULATED IF COMPOSITE IF
INTERFERENCE
IF FILTER
DIGITIZED IF
BERT
DATA AND CLOCK
PC
RS232
CONTROL/STATUS
LOGIC
TEST
HSP50110/210EVAL
EVALUATION BOARD
AND A/D
ANALYZER
DATA
FIGURE 3. TYPICAL DEMODULATOR PERFORMANCE EVALUTAION CONFIGURATION
HSP50110/210EVAL