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Appendices A through H contain detailed information about
Circuit Board Layout, Initial Jumper Settings, Connector Pin
Assignments, Test Header Pin definitions, Detailed Sche-
matics, Parts List, Memory Maps and a Descriptive File List.

Control/Status Software Program

The Control/Status software program, written for DOS based
PC’s, is included in the evaluation kit. This software supports
operation of the evaluation circuit board in basic PSK
demodulator and phased locked loop (PLL) configurations.
The menu driven software program allows the user to select
a variety of demodulator and data path configurations. It cal-
culates demodulator/PLL configuration data based on the
user menu selections, downloads configuration data to the
evaluation circuit board and displays operational status. The
calculated configuration data are the register values for the
IC’s on the evaluation board. This data is downloaded to the
evaluation circuit board microcontroller using the COM1 or
COM2 serial port on the PC. Status is read from circuit
board registers using the same serial interface and dis-
played on the computer screen. The downloaded configura-
tion data is available in a text file to facilitate editing, printing,
or exporting. Additionally, the software can configure the
HSP43124 FIR filter by importing .RPT files generated using
SERINADE, a Harris filter design application.

The Control/Status software MAIN MENU offers six sub-
menus for various configuration selections and three com-
mand actions. The menu tree is illustrated in Figure 2.

The six configuration submenus are:

• Data Path/Modulation Setup Menu

• Carrier Tracking Loop Setup Menu

• Bit Synchronization Loop Setup Menu

• Acquisition/Tracking Setup Menu

• Configure Hardware Menu

• Generate Output Files

The three command actions are:

• Load Configuration File
• Save Configuration File
• Exit

A typical operational sequence is:

A. Load Configuration File.

Executing this MAIN MENU item brings up a screen with the
current file name and requests the name of the file to be
loaded. Once the new filename name is entered, this command
loads the configuration setup and returns to the MAIN MENU
screen. This command allows the user to select a previously
saved configuration file for display, review and editing.

B. Edit Configuration File.

This is done by sequencing through each of the configura-
tion submenus and adjusting the parameters for the desired
hardware configuration.

- The DATA PATH/MODULATION SETUP MENU is used

to select clock rates, modulation type, filtering, signal
levels, SNR range and I/O formats.

- The CARRIER TRACKING LOOP SETUP MENU is

used to select loop bandwidth, loop filter order, damping
coefficient, sweep rate, and limits for both Carrier acqui-
sition and tracking.

- The BIT SYNC LOOP SETUP MENU is used to select

loop bandwidth, loop filter order, damping coefficient,
and limits for both Bit Timing tracking and acquisition.

- The ACQUISITION AND TRACKING SETUP MENU is

used to select lock detection integration time, lock
detection thresholds and other acquisition and tracking
parameters.

C. Save Configuration File

Executing this MAIN MENU item brings up a screen with the
current file name and a request for a filename to be saved.
Once the new filename name is entered, this command
stores the configuration setup to the new file.

DATA PATH/

MODULATION

SETUP MENU

MAIN MENU

CARRIER

BIT SYNC

ACQUISITION

(5) LOAD CONFIGURATION FILE

(6) SAVE CONFIGURATION FILE

GENERATE

CONFIGURE

(9) EXIT

TRACKING LOOP

SETUP MENU

LOOP

SETUP MENU

HARDWARE

MENU

AND

TRACKING

SETUP MENU

OUTPUT FILES
REVIEW MENU

(1)

(2)

(3)

(4)

(7)

(8)

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

ENTER

NEW

VALUE

MENU

(1)

(27)

(1)

(1)

(1)

(1)

(15)

(8)

(10)

(5)

FIGURE 2. MENU TREE FOR THE CONTROL/STATUS SOFTWARE

HSP50110/210EVAL

Summary of Contents for HSP50210EVAL

Page 1: ...tions of the evaluation circuit board The circuit board is a 3U x 160mm VME Eurocard form factor with dual 96 pin I O connectors The connector pinouts conforms to the VME P2 connector pinout i e power...

Page 2: ...File Exit A typical operational sequence is A Load Configuration File Executing this MAIN MENU item brings up a screen with the current file name and requests the name of the file to be loaded Once th...

Page 3: ...ntroller control signals A microprocessor RESET function can be implemented by installing a normally open push button switch across pins 9 and 10 of JP6 Header JP7 contains the RS232 connection to the...

Page 4: ...any adjustments to the parameters by entering the desired item number and editing it 7 ___ Repeat Steps 5 and 6 for MAIN MENU items 2 3 and 4 These Menus should match the items found in Figures 6 7 a...

Page 5: ...k 0 01 6 Carrier Tracking Loop Damping 0 707 7 AFC Disabled 8 Frequency Error Gain Acq n a Hz Hz 9 Frequency Error Gain Trk n a Hz Hz 10 Delay in Discriminator 0 5 baud 11 Acquisition Sweep Rate 5 Hz...

Page 6: ...d Cosine Filter Several filter coefficient files have been included on the HSP50110 210EVAL disk because the SERINADE program does not compute square root of raised cosine filters These files are prov...

Page 7: ...Three ACT86 gates U3 isolate the on board and off board clock signals allow different polarities for the clocks and provide the 3 0V minimum VIH required by the HSP parts Installing a jumper between...

Page 8: ...TO JP2 1 JP2 2 JP2 3 JP2 4 JP2 5 JP2 6 JP2 7 JP2 8 JP2 9 JP2 10 JP2 29 JP2 30 JP4 1 JP4 2 JP4 3 JP4 4 JP4 5 JP4 6 JP4 7 JP4 8 P1 HSP50110 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 P2 HSP50210 HSP43124...

Page 9: ...N C B28 N C C28 N C A29 N C B29 N C C29 N C A30 N C B30 N C C30 GND A31 N C B31 GND C31 N C A32 N C B32 5V C32 N C P2 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL PIN SIGNAL PIN SIGNAL A1 N C B1 5V C1 GND A2...

Page 10: ...30 GND Ground 31 AGCLVL A D Input to 68HC11 32 GND Ground JP2 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 DQTPH1 DQT Phase Shift Bit1 3 GND Ground 4 DQTPH...

Page 11: ...BB1 Q Baseband 1 26 QBB0 Q Baseband Bit 0 LSB 27 GND Ground 28 GND Ground 29 BBDRDY DCL Input Enable 30 GND Ground 31 AGCLVL A D Input to 68HC11 32 GND Ground JP4 TEST HEADER PIN ASSIGNMENTS PIN SIGNA...

Page 12: ...GND Ground 28 GND Ground 29 DATACLK Output Symbol Clock 30 GND Ground 31 GPOUT Jumper to Pin 29 to Connect DATACLK to P2 32 GND Ground JP6 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNA...

Page 13: ...s Bit 1 25 PA2 6811 Address Bit 2 26 PA3 6811 Address Bit 3 27 PA4 6811 Address Bit 4 28 PA5 6811 Address Bit 5 29 PA6 6811 Address Bit 6 30 PA7 6811 Address Bit 7 31 GND Ground 32 GND Ground 33 PA8 6...

Page 14: ...14 Appendix E Detailed Schematics HSP50110 210EVAL...

Page 15: ...15 HSP50110 210EVAL...

Page 16: ...16 HSP50110 210EVAL...

Page 17: ...17 HSP50110 210EVAL...

Page 18: ...18 HSP50110 210EVAL...

Page 19: ...19 HSP50110 210EVAL...

Page 20: ...20 HSP50110 210EVAL...

Page 21: ...21 HSP50110 210EVAL...

Page 22: ...22 HSP50110 210EVAL...

Page 23: ...23 HSP50110 210EVAL...

Page 24: ...24 HSP50110 210EVAL...

Page 25: ...25 HSP50110 210EVAL...

Page 26: ...6 7 8 3 16 PTC30DAAN Conn 2 x 30 Pin Header SULLINS JP9 1 17 PTC25DAAN Conn 2 x 25 Pin Header SULLINS JP1 5 5 18 510AG91D20ES Socket SIP Socket 20 Pin AUGAT XU4 5 13 6 19 814 AG11D Socket DIP Socket 1...

Page 27: ...R Registers 4208 42FF Unused 248 Bytes 4300 44FF QFIR Coefficients 4500 4507 QFIR Registers 4508 45FF Unused 248 Bytes 4600 467F DCL Registers 00 31d MSB FIRST 4680 46FF Unused 128 Bytes 4700 471F DQT...

Page 28: ...e Generated by DMDEVAL4 EXE Containing Coefficients for the HSP43124 Both Channels PROGRAM EXECUTION FILE DESCRIPTION FILENM Holds File Prefix for Last Configuration Saved Loaded on Start up modified...

Page 29: ...QPSK 3 OQPSK 4 8PSK Item 8 Baud Rate 1 to 56 000 000 Symbols s This is the output symbol rate of the HSP50210 Note that entering a value greater than one half the clock rate induces excessive aliasing...

Page 30: ...ate for the AGC in the HSP50210 This AGC adjusts for changes in signal level due to SNR changes or signals coming and going inside the filter band of the HSP50110 This AGC is typically set to slew slo...

Page 31: ...elay chosen The delay can be set to 1 2 4 8 or 16 samples 0 5 1 2 4 or 8 baud intervals Item 11 Acquisition Sweep Rate 0Hz baud to 1 000 000Hz baud This is the amount that the lag accumulator is incre...

Page 32: ...clock The master clock slower clock selection is done here and the speed of the slower clock slow clock is selected in menu item 14 of the carrier loop menu If the tracking is done via the HSP50110 t...

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