5
The hardware is now configured as a 128 KBPS BPSK
demodulator with root raised cosine data filters. The Con-
trol/Status software is now configured to report status to the
screen so that you can evaluate the performance of the
demodulator configuration.
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HSP50110/210 EVALUATION BOARD SOFTWARE
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DATA PATH / MODULATION MENU
Current File Name.\B128RRC
(1) Master Clock Freq. . . . . . . . . . . . . . . . . . . . . . .40000000 Hz
(2) Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . .40000000 Hz
(3) Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gated
(4) DQT Input Samples. . . . . . . . . . . . . . . . . . . . . .Real
(5) DQT Input Format. . . . . . . . . . . . . . . . . . . . . . .Offset Bin
(6) L.O. Center Freq.. . . . . . . . . . . . . . . . . . . . . . . .+5000000 Hz
(7) Data Modulation . . . . . . . . . . . . . . . . . . . . . . . .BPSK
(8) Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128000 Hz
(9) DQT Output Rate . . . . . . . . . . . . . . . . . . . . . . .256000 Hz
(10) I.F. NBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750000 Hz
(11) DQT Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .CIC w/ comp
(12) DCL RRC Filter . . . . . . . . . . . . . . . . . . . . . . .Enabled
(13) DCL I&D. . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bypassed
(14) HSP43124 . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bypassed
(15) Es/No (min) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0 dB
(16) Es/No (max . . . . . . . . . . . . . . . . . . . . . . . . . . .+100 dB
(17) Es/No (design) . . . . . . . . . . . . . . . . . . . . . . . . .+6 dB
(18) A/D backoff (min.) . . . . . . . . . . . . . . . . . . . . .12 dB
(19) A/D backoff (max.) . . . . . . . . . . . . . . . . . . . . .18 dB
(20) DCL Output Vector . . . . . . . . . . . . . . . . . . . . . -6 dBFS
(21) DQT Output Level . . . . . . . . . . . . . . . . . . . . . -12 dBFS
(22) DCL Detect. Level . . . . . . . . . . . . . . . . . . . . . -12 dBFS
(23) Slicer Threshold. . . . . . . . . . . . . . . . . . . . . . . . 0.25
(24) DQT AGC Slew Rate . . . . . . . . . . . . . . . . . . . 30 dB/sec
(25) DCL AGC Slew Rate . . . . . . . . . . . . . . . . . . .10 dB/sec
(26) AGC Limits . . . . . . . . . . . . . . . . . . . . . . . . . . .FULL RANGE
(27) Output Mux Control . . . . . . . . . . . . . . . . . . . . 7
(0) MAIN MENU
ENTER SELECTION:
FIGURE 5. DATA PATH/MODULATION MENU
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HSP50110/210 EVALUATION BOARD SOFTWARE
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CARRIER TRACKING LOOP MENU
(1) Carrier Tracking Loop Upper Limit . . . . . . . . +30000 Hz
(2) Carrier Tracking Loop Lower Limit. . . . . . . . -30000 Hz
(3) Carrier Tracking. . . . . . . . . . . . . . . . . . . . . . . . 2nd order
(4) Carrier Fractional Loop BW (Acq) . . . . . . . . 0.03
(5) Carrier Fractional Loop BW (Trk. . . . . . . . . . 0.01
(6) Carrier Tracking Loop Damping . . . . . . . . . . 0.707
(7) AFC.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabled
(8) Frequency Error Gain (Acq) . . . . . . . . . . . . . . n/a Hz/Hz
(9) Frequency Error Gain (Trk) . . . . . . . . . . . . . . n/a Hz/Hz
(10) Delay in Discriminator . . . . . . . . . . . . . . . . . 0.5 baud
(11) Acquisition Sweep Rate . . . . . . . . . . . . . . . . 5 Hz/baud
(12) Carrier Tracking Bits to DQT. . . . . . . . . . . . 32
(13) Carrier Tracking . . . . . . . . . . . . . . . . . . . . . . Lead & Lag to DQT
(14) DCL Serial Output Clock (SerClk) . . . . . . . Fclk/8
(15) Carrier Serial Output @ . . . . . . . . . . . . . . . . Fclk
(0) MAIN MENU
ENTER SELECTION:
FIGURE 6. CARRIER TRACKING LOOP MENU
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HSP50110/210 EVALUATION BOARD SOFTWARE
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BIT SYNC LOOP MENU
(1) Bit Sync Loop Upper Limit . . . . . . . . . . . . . . .+500 Hz
(2) Bit Sync Loop Lower Limit . . . . . . . . . . . . . . .-500 Hz
(3) Symbol Tracking . . . . . . . . . . . . . . . . . . . . . . . .2nd order
(4) Bit Sync Fractional Loop BW (Acq) . . . . . . . . 0.01
(5) Bit Sync Fractional Loop BW (Trk . . . . . . . . . 0.003
(6) Bit Sync Loop Damping . . . . . . . . . . . . . . . . . . 1
(7) Symbol Tracking Bits . . . . . . . . . . . . . . . . . . . .32
(8) Bit Sync Serial Output @ . . . . . . . . . . . . . . . . . Fclk
(0) MAIN MENU
ENTER SELECTION:
FIGURE 7. BIT SYNC LOOP MENU
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HSP50110/210 EVALUATION BOARD SOFTWARE
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ACQUISITION / TRACKING (LOCK DETECTION) MENU
(1) Lk Det Integ. Time (ACQ) . . . . . . . . . . . . . . . .96 symbols
(2) Lk Det Integ. Time (TRK) . . . . . . . . . . . . . . . .512 symbols
(3) Lk Det Threshold (ACQ) . . . . . . . . . . . . . . . . .40 deg.
(4) Lk Det Threshold (TRK) . . . . . . . . . . . . . . . . .43 deg.
(5) Lock Verify Cycles (TRK Integ. times) . . . . . . 8
(6) False Lock / Freq Error Integ . . . . . . . . . . . . . .False Lock
(7) False Lock Detector. . . . . . . . . . . . . . . . . . . . . . Disabled
(8) False Lock Threshold . . . . . . . . . . . . . . . . . . . .45
(9) False Lock Sweep Count . . . . . . . . . . . . . . . . . 8
(10) Acquisition Type . . . . . . . . . . . . . . . . . . . . . . .Swept
(0) MAIN MENU
ENTER SELECTION:
FIGURE 8. ACQUISITION/TRACKING (LOCK DETECTION)
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HSP50110/210 EVALUATION BOARD SOFTWARE
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HARDWARE INTERFACE MENU
(1) Full Initialization
(2) Load filename.ary Registers to Board
(3) Load filter.ary FIR coefs to Board
(4) Turn Status Display ON
(5) Change one register
(0) MAIN MENU
ENTER SELECTION:
FIGURE 9. HARDWARE INTERFACE MENU
HSP50110/210EVAL
Summary of Contents for HSP50210EVAL
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