Harris HSP50210EVAL User Manual Download Page 27

27

Appendix G

Memory Maps

HARDWARE AND SOFTWARE

MEMORY MAP

FIRST
ADDR

LAST

ADDR

DESCRIPTION

0000

 007F

 68HC11 Configuration Registers

0080

02FF

 68HC11 Internal RAM B

0300

037F

 68HC11 Internal RAM A

0D80

0FFF

 68HC11 Internal EEPROM

 HARDWARE ADDRESS DECODER 1

1400

14FF

IFIR (HSP43124)
(1400-1407 R/W)

1500

15FF

QFIR (HSP43124)
(1500-1507 R/W)

1600

16FF

DQT (HSP50110)
(1600-1604 W, 1600 R)

1700

17FF

DCL (HSP50210)
(1700-1705 W, 1700-1704 R)

HARDWARE ADDRESS DECODER 2

2000

21FF

WRSTRB1 (on JP9)

2200

23FF

WRSTRB2 (on JP9)

2400

27FF

WRSTRB3 (Not Connected)

EXTERNAL RAM (8K BYTES)

4000

5FFF

RAM

68HC11 INTERNAL EPROM

A000

CFFF

Unused

D000

FFFF

MOTOROLA BUFFALO
Monitor Program
(Version BUFK42)

RAM USAGE BY DEMODEVB.EXE PROGRAM

(2352/8192 BYTES USED)

ADDRESS

DESCRIPTION

4000-41FF

IFIR Coefficients

4200-4207

IFIR Registers

4208-42FF

Unused (248 Bytes)

4300-44FF

QFIR Coefficients

4500-4507

QFIR Registers

4508-45FF

Unused (248 Bytes)

4600-467F

DCL Registers 00-31d
MSB FIRST

4680-46FF

Unused (128 Bytes)

4700-471F

DQT Registers 00-07
MSB First

4720-47FF

Unused (224 Bytes)

4800-4FFF

Unused (2048 Bytes)

5000-502F

DQT Write Program

5030-50FF

Unused (192 Bytes)

5100-51B2

DCL Write Program

51BF-51FF

Unused (64 Bytes)

5200-526

IFIR Write Program

5270-52FF

Unused (144 Bytes)

5300-536F

QFIR Write Program

5370-53FF

Unused (144 Bytes)

5400-546F

DCL Status Program

5680-569F

Status Registers

56A0-5FFF

Unused (2400 Bytes)

68HC11 CONFIGURATION REGISTER

PROGRAMMING

ADDR

 NAME

DATA

 COMMENT

005A

 CSCTR

00h

No CS Cycle Stretching

005B

CSCTL

88h

EN, Active Low, Sync to E, 4K Block GP Priority, Bit 7 GP

005C

GPCS1A

 08h

Address Start at 4000h

005D

GPCS1C

 03h

No CS Interaction, Active Low, Sync TO E, 8K Block

005E

GPCS2A

 04h

Address Start at 2000h

005F

GPCS2C

 01h

No CS Interaction, Active Low, Sync TO E, 2K Block

HSP50110/210EVAL

Summary of Contents for HSP50210EVAL

Page 1: ...tions of the evaluation circuit board The circuit board is a 3U x 160mm VME Eurocard form factor with dual 96 pin I O connectors The connector pinouts conforms to the VME P2 connector pinout i e power...

Page 2: ...File Exit A typical operational sequence is A Load Configuration File Executing this MAIN MENU item brings up a screen with the current file name and requests the name of the file to be loaded Once th...

Page 3: ...ntroller control signals A microprocessor RESET function can be implemented by installing a normally open push button switch across pins 9 and 10 of JP6 Header JP7 contains the RS232 connection to the...

Page 4: ...any adjustments to the parameters by entering the desired item number and editing it 7 ___ Repeat Steps 5 and 6 for MAIN MENU items 2 3 and 4 These Menus should match the items found in Figures 6 7 a...

Page 5: ...k 0 01 6 Carrier Tracking Loop Damping 0 707 7 AFC Disabled 8 Frequency Error Gain Acq n a Hz Hz 9 Frequency Error Gain Trk n a Hz Hz 10 Delay in Discriminator 0 5 baud 11 Acquisition Sweep Rate 5 Hz...

Page 6: ...d Cosine Filter Several filter coefficient files have been included on the HSP50110 210EVAL disk because the SERINADE program does not compute square root of raised cosine filters These files are prov...

Page 7: ...Three ACT86 gates U3 isolate the on board and off board clock signals allow different polarities for the clocks and provide the 3 0V minimum VIH required by the HSP parts Installing a jumper between...

Page 8: ...TO JP2 1 JP2 2 JP2 3 JP2 4 JP2 5 JP2 6 JP2 7 JP2 8 JP2 9 JP2 10 JP2 29 JP2 30 JP4 1 JP4 2 JP4 3 JP4 4 JP4 5 JP4 6 JP4 7 JP4 8 P1 HSP50110 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 P2 HSP50210 HSP43124...

Page 9: ...N C B28 N C C28 N C A29 N C B29 N C C29 N C A30 N C B30 N C C30 GND A31 N C B31 GND C31 N C A32 N C B32 5V C32 N C P2 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL PIN SIGNAL PIN SIGNAL A1 N C B1 5V C1 GND A2...

Page 10: ...30 GND Ground 31 AGCLVL A D Input to 68HC11 32 GND Ground JP2 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 DQTPH1 DQT Phase Shift Bit1 3 GND Ground 4 DQTPH...

Page 11: ...BB1 Q Baseband 1 26 QBB0 Q Baseband Bit 0 LSB 27 GND Ground 28 GND Ground 29 BBDRDY DCL Input Enable 30 GND Ground 31 AGCLVL A D Input to 68HC11 32 GND Ground JP4 TEST HEADER PIN ASSIGNMENTS PIN SIGNA...

Page 12: ...GND Ground 28 GND Ground 29 DATACLK Output Symbol Clock 30 GND Ground 31 GPOUT Jumper to Pin 29 to Connect DATACLK to P2 32 GND Ground JP6 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNA...

Page 13: ...s Bit 1 25 PA2 6811 Address Bit 2 26 PA3 6811 Address Bit 3 27 PA4 6811 Address Bit 4 28 PA5 6811 Address Bit 5 29 PA6 6811 Address Bit 6 30 PA7 6811 Address Bit 7 31 GND Ground 32 GND Ground 33 PA8 6...

Page 14: ...14 Appendix E Detailed Schematics HSP50110 210EVAL...

Page 15: ...15 HSP50110 210EVAL...

Page 16: ...16 HSP50110 210EVAL...

Page 17: ...17 HSP50110 210EVAL...

Page 18: ...18 HSP50110 210EVAL...

Page 19: ...19 HSP50110 210EVAL...

Page 20: ...20 HSP50110 210EVAL...

Page 21: ...21 HSP50110 210EVAL...

Page 22: ...22 HSP50110 210EVAL...

Page 23: ...23 HSP50110 210EVAL...

Page 24: ...24 HSP50110 210EVAL...

Page 25: ...25 HSP50110 210EVAL...

Page 26: ...6 7 8 3 16 PTC30DAAN Conn 2 x 30 Pin Header SULLINS JP9 1 17 PTC25DAAN Conn 2 x 25 Pin Header SULLINS JP1 5 5 18 510AG91D20ES Socket SIP Socket 20 Pin AUGAT XU4 5 13 6 19 814 AG11D Socket DIP Socket 1...

Page 27: ...R Registers 4208 42FF Unused 248 Bytes 4300 44FF QFIR Coefficients 4500 4507 QFIR Registers 4508 45FF Unused 248 Bytes 4600 467F DCL Registers 00 31d MSB FIRST 4680 46FF Unused 128 Bytes 4700 471F DQT...

Page 28: ...e Generated by DMDEVAL4 EXE Containing Coefficients for the HSP43124 Both Channels PROGRAM EXECUTION FILE DESCRIPTION FILENM Holds File Prefix for Last Configuration Saved Loaded on Start up modified...

Page 29: ...QPSK 3 OQPSK 4 8PSK Item 8 Baud Rate 1 to 56 000 000 Symbols s This is the output symbol rate of the HSP50210 Note that entering a value greater than one half the clock rate induces excessive aliasing...

Page 30: ...ate for the AGC in the HSP50210 This AGC adjusts for changes in signal level due to SNR changes or signals coming and going inside the filter band of the HSP50110 This AGC is typically set to slew slo...

Page 31: ...elay chosen The delay can be set to 1 2 4 8 or 16 samples 0 5 1 2 4 or 8 baud intervals Item 11 Acquisition Sweep Rate 0Hz baud to 1 000 000Hz baud This is the amount that the lag accumulator is incre...

Page 32: ...clock The master clock slower clock selection is done here and the speed of the slower clock slow clock is selected in menu item 14 of the carrier loop menu If the tracking is done via the HSP50110 t...

Reviews: